Xilinx intros 3 IP cores for 3G+/4G base stations

BANGALORE, INDIA: Xilinx Inc. announced the availability of three IP cores for 3G+/4G wireless base stations. The three new products are - Serial RapidIO Gen 2 v1.2 Endpoint LogiCore IP, JESD204 v1.1 LogiCore IP , and CPRI v4.1 LogiCore IP.

The  Serial RapidIO Gen 2 v1.2 Endpoint LogiCore IP is based on RapidIO Trade Association’s RapidIO Gen 2.2 specification and supports line rates of up to 6.25G in 1x/2x/4x lane widths.

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Comprised of Serial RapidIO Physical Layer core and a Logical (I/O) and Transport layer core, this IP core is supported by 7 series and Virtex-6 FPGAs and comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design.

The  CPRI v4.1 LogiCore IP is designed to the Common Public Radio Interface (CPRI) standard specification v4.2.

Supported by 7 series FPGAs, Xilinx CPRI v4.1 LogiCore IP doubles the connectivity to the remote radio heads to 9.8G to enhance system data capacity, claims the company in a release.

The JESD204 v1.1 LogiCORE IP is based on Joint Electron Devices Engineering Council (JEDEC) JESD204B standard and is supported by 7 series FPGAs, this IP core can be configured as JESD204B transmitter for interfacing to DAC device or JESD204B Receiver for interfacing to ADC device.

The Serial RapidIO Gen 2 v1.2, CPRI v4.1, and JESD204B v1.1 LogiCore IP cores are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.