Xilinx introduces latest version of ISE design suit

SAN FRANCISCO, USA: Xilinx Inc has introduced a latest version of its ISE Design Suite to support both its Virtex-6 and Spartan-6 FPGA families.

As per the company, ISE 12 adds intelligent clock gating technology, advances in timing-driven design preservation, AMBA 4 AXI4-compliant IP support and simple to use partial reconfiguration capabilities.

According to Xilinx, the intelligent clock-gating technology decreases dynamic power consumption by to the extent of 30 percent. Xilinx said the technology mechanically detects and neutralizes avoidable transitions with fine grain optimizations, using algorithms that evaluate designs, identifying elements that do not vary downstream logic and communicate when toggled.

According to Hitesh Patel, director of ISE foundation product marketing at Xilinx, the intelligent clock gating technology is most appropriate for encryption and other computationally intensive designs.

Patel said ISE 12 in addition features a productized design flow for Xilinx' partial reconfiguration technology that will build the technology user to utilize.

When asked if the easiness of use improvements will prompt further users to execute partial reconfiguration, Patel said, "I think it's at a point where a lot more people will say, 'let me try this on my design.'"

ISE 12 also adds advanced design preservation capabilities to enable designers to reach design closure fast with repeatable timing results, according to Xilinx.

The tool lets designers partition designs to focus on achieving timing for critical blocks, then lock those blocks to preserve placement and routing while they work on the rest of the design, Xilinx said.

The company said that Xilinx is rolling out ISE 12 in stages, with intelligent clock gating for Virtex-6 designs shipping currently with the 12.1 release. Xilinx said The part reconfiguration enhancements will be offered in the 12.2 release, set for summer, whilst AXI4 IP support will trail with the 12.3 release in the fall.

As per Xilinx, the 12.1 software features an average of 2X faster logic synthesis and 1.3X faster implementation run times for big designs than earlier versions and an enhanced embedded design method.

Xilinx said that the list price for ISE 12.1 begins at $2,995 for the Logic Edition. clients can download full-featured 30-day evaluation versions at no charge from the web site.