Two-chip IF soln

Features: Analog Devices Inc. has introduced a two-chip IF (intermediate frequency) receiver solution that improves the data bandwidth and capacity of next-generation, multi-carrier wireless base stations compatible with emerging 3G cellular transmission standards.

Analog Devices said in a statement that its dual-channel AD8376 VGA (variable gain amplifier) and AD6655 IF diversity receiver solution replaces 48 discrete components, enabling 3G micro- and pico-cell base stations with dramatically reduced power consumption and physical volume. Each radio channel can handle up to six carriers. The new VGA and IF diversity receiver also increase automatic gain-control loop performance by 100 times existing options, which improves base station receiver sensitivity and dynamic range and ensures both weak and strong incoming cell phone call signals are quickly and effectively received and processed.

The AD8376 dual-channel VGA provides precise fine-gain-step adjustment for digital radio receivers. The device features a bandwidth of 600 MHz, supporting high IF sampling receiver architectures within cellular and broadband WiMAX receivers. An independent 5-pin digital interface allows the user to take advantage of a 24dB gain range and 1dB gain-step resolution. The AD8376 is designed to replace discrete attenuator and IF amplifiers, offering considerable board and package density savings. With 50dBm output IP3 on 130mA of quiescent current on a +5volt supply, current consumption is also significantly reduced.

The AD6655 integrates many of the functions required for diversity receive path in a single device, including an ultra-low-latency peak detector and an rms signal power monitor that can be used in conjunction with the AD8376 and logic to form a flexible AGC. In addition, the AD6655 includes the industry’s fastest 14-bit ADC (analog-to-digital converter), at 150 MSPS (million samples per second), followed by a DDC (digital down converter). The DDC functionality includes a 32-bit NCO (numerically controlled oscillator), a decimating half-band filter and an output FIR (finite-impulse response) filter. Together, these provide an effective bandpass filtering function and reduce the output rate, which yields an SNR (signal-to-noise ratio) of 75 dB at 70 MHz, an improvement of 2.5 dB over the typical ADC. By integrating the DDC with the ADC, designers realize a significant reduction in board space while eliminating the high-speed interconnect problems usually found on system boards when the devices are implemented separately.

The AD6655 is offered in both 12- (AD6653) and 14-bit resolutions with sample rates of 80 MSPS, 105 MSPS, 125 MSPS and 150 MSPS. For applications that require only the dual-ADC function without the DDC, the recently announced AD9640 is pin compatible and includes signal monitor, level detection, and 1-to-8 clock divider.

A single-channel version, the AD8375, is sampling now with full production also scheduled for June 2007.

Price: The AD8376 is priced at $6.25 per unit in 1,000-piece quantities and is housed in a 32-lead LFCSP (lead-frame chip-scale package) and the AD8375 is priced at $4.25 per unit in 1,000-piece quantities and is housed in a 24-lead LFCSP.