Toshiba standardizes on CCS technology at 65nm

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Toshiba has standardized on the open source Liberty Composite Current Source (CCS) modeling technology for its CMOS5/TC320C 65nm production libraries.

Using these high accuracy libraries within Synopsys' Galaxy Design Platform, Toshiba engineers can improve system-on-chip (SoC) design by minimizing guard-band margins during design implementation and sign-off. The powerful CCS voltage and temperature scaling technology further boosts designer productivity by simplifying low power design flows.

"During our early stages of 65nm flow development, it was clear to us that current source modeling was necessary," said Takashi Yoshimori, technology executive of SoC Design, Semiconductor Company, Toshiba. "We extensively evaluated CCS along with other current source formats. CCS was able to meet our criteria for stringent accuracy and scaling requirements. CCS tightened the delay calculation accuracy by over two-fold from 5 percent vs. the HSPICE simulation tool to 2 percent. Furthermore, the voltage and temperature scaling capabilities makes CCS very adaptable, simplifying design flows, especially for multi-voltage designs. This improves our designer productivity and reduces the number of library corners and characterization cost."

CCS modeling technology, part of the open-source Liberty library modeling standard, enables highly accurate and comprehensive modeling of nanometer effects that encompass timing, signal-integrity, and power. CCS modeling technology enables voltage variation modeling, simplifying advanced low-power design flows such as multi-Vt and multi-Vdd as well as dynamic voltage and frequency scaling.

CCS is fully supported throughout Synopsys' Galaxy Design Platform. There is significant industry-wide momentum behind CCS modeling technology with libraries available from leading foundries, intellectual property vendors and integrated device manufacturers.

IBM to port Synopsys DesignWare USB 2.0 nanoPHY IP

Synopsys also announced an agreement with IBM to port the Synopsys DesignWare USB 2.0 nanoPHY IP to the 45nm Common Platform process. This agreement further strengthens the collaboration between the companies to provide USB PHY IP for IBM's leading process technologies, including 130-, 90- and 65-nm, all of which are silicon-proven, USB logo-certified and in volume production. Synopsys is the first IP provider to announce the development of a mixed-signal USB 2.0 PHY IP targeting this 45-nm process technology.

The Synopsys DesignWare USB 2.0 nanoPHY IP will be designed with Common Platform technology design rules to provide GDSII compatibility between Common Platform technology manufacturers. The IP is targeted for a broad range of high-volume, low-power mobile and consumer applications where the key requirements include minimal area and low power consumption.

The DesignWare USB 2.0 nanoPHY addresses these key requirements by implementing an architecture that provides a highly effective combination of small area, low power consumption and low leakage. In addition, the DesignWare USB 2.0 nanoPHY IP has unique built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify the existing design. This feature enables designers to increase yield and minimize the cost of expensive silicon re-spins.