Synopsys, TSMC ally on 40nm HSPICE modeling

MOUNTAIN VIEW, USA: Synopsys Inc. has released the TSMC Modeling Interface (TMI) methodology, developed from Synopsys' production-proven protocol for integrating custom device models into HSPICEÂ, HSIM„ and NanoSim transistor-level circuit simulators.

The TMI methodology delivers an innovative and efficient device modeling approach for TSMC's process technologies at 40 nanometers (nm) and below. This new methodology, on average, improves simulation time and reduces memory usage by 5X.

With device geometries shrinking at every new process node, MOSFET model complexity has increased in order to accurately represent the impact of new physical effects. At 40nm, the industry-standard BSIM-4 MOSFET model must now take into consideration mechanical stress effects in silicon, and layout dependencies that alter the characteristics of individual device instances based on their placement and proximity to other devices.

Standardization of the stress-effect modeling is extremely difficult because of the differences that exist in each application of strain engineering, and requires customization of models for every process.

"Our technology partnership with TSMC delivers an order-of-magnitude improvement in simulation time-to-results, and is of tremendous benefit to our mutual customers using TSMC's 40-nanometer technology node," said Paul Lo, senior vice president and general manager of the Analog/Mixed Signal Group at Synopsys. "The success of this joint effort with TSMC has again demonstrated Synopsys' commitment to provide the most advanced device modeling and circuit simulation performance for the latest generation of silicon technology. In addition, the TMI methodology, based on Synopsys' protocols, establishes the foundation for TSMC's SPICE Tool Qualification Program, which we anticipate will become an industry standard."