ST, Soitec to develop 300mm wafer-level BSI technology

GRENOBLE, FRANCE: STMicroelectronics and Soitec announced an exclusive joint co-operation that will lead to the development of 300mm wafer-level backside-illumination (BSI) technology for next-generation image sensors in consumer products.

The resolution of today’s leading-edge image sensors is continuously increasing, while demand is high for the overall reduction of the camera-module footprint, particularly in consumer markets. This means the necessary development of smaller individual pixel sizes, while maintaining pixel sensitivity to produce high-quality images. Backside illumination is a key enabling technology to meet this challenge in the development of next-generation image sensors.

The agreement between the two companies includes the licensing by Soitec to ST of the Smart Stacking bonding technology for the manufacturing of backside-illumination sensors on 300mm wafers. This technology, developed by Soitec’s Tracit business unit, leverages molecular bonding, and mechanical, as well as chemical thinning.

ST will develop a new generation of image sensors based on its advanced derivative-CMOS process technology at 65nm and beyond, at its 300mm facility in Crolles, France. In combination with ST’s advanced wafer-level manufacturing capabilities, the Smart Stacking technology will enable ST to increase its leadership in developing and supplying high-performance image sensors for mobile consumer products.