SHF memory IP targets advanced process node designs

OTTAWA, USA: Sidense Corp., a leading developer of non-volatile memory OTP IP cores, announced that its SHF Non-Volatile Memory (NVM) macros have met stringent JEDEC accelerated testing requirements for TSMC's 28HPM and 28HPL process nodes.

The 28nm HPM node addresses applications requiring high speed as well as low-leakage power and is suitable for many applications from networking and tablets to mobile consumer products. The 28nm HPL low-power node is best suited for cellular baseband, application processor, wireless connectivity, and programmable logic applications.

To meet JEDEC standard reliability test requirements, three lots of SHF devices at each process node underwent 1000 hours of high temperature storage (HTS) and high temperature operating life (HTOL) stress testing with no bit-cell failures. For both process nodes, macro functionality and performance was verified across each of the FF, FS, SF, SS, and TT process corners at read and program temperatures of -40°C to +125°C. All macro configurations were successfully programmed and read in single-ended, redundant and double-redundant read modes.

"Our patented 1T-Fuse bit-cell architecture allows us to migrate Sidense 1T-OTP macros to shrinking process nodes as they become available," said Rhéal Gervais, Sidense VP of Operations. "We perform rigorous characterization and qualification of our macros at each node and process variant, including JEDEC accelerated testing, to assure our customers that they are getting low-power non-volatile memory that is highly reliable."