Sequence to host 2nd annual Design for Power seminar

SANTA CLARA, USA & BANGALORE, INDIA: Sequence Design, EDA's Design-For-Power (DFP) technology leader, is taking its popular low-power design seminar to Bangalore again on September 19, 2007. The DFP seminar will be held at The Taj Residency, Bangalore, starting 9AM, and will conclude with a complimentary luncheon. The event is co-sponsored by Sequence and D'gipro, the distributor for Sequence products for the India market.

Sequence presentations and invited speakers will focus on three areas: predicting power consumption early in the design cycle, reduction of switching power consumption, and reduction of leakage power.

The agenda of this seminar is:

-- Vic Kulkarni, President & CEO, Sequence Design: Sequence Design For Power Update and Strategy

-- Keynote: Dr Satya Gupta, VP Engineering, Open Silicon: Power Challenges in Advanced Process Node

-- Anurag Seth, Engineering Group Director - IC Digital, Cadence: Advanced Low Power Design Using CPF

-- Bharadwaj Amurtur, Assistant Professor, IISc Bangalore: Recent Advances in Leakage Management

-- PowerTheater Success Presentation by Indian Semiconductor Company

-- Rahul Prasad, Sr. Manager, Applications and Customer Support, Sequence Design: Sequence DFP Flow

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets.

In the past five years, Sequence has invested over $5 million in its India-based R&D operations alone. The company has a growing customer base of multinational semiconductor companies in India, particularly in Bangalore's technology-rich environment, and has recently expanded its "Center of Excellence" in Noida's Logix Techno Park.