Sequence chops power @ Axell

SANTA CLARA, USA: Axell Corp., an emerging Japanese multimedia chip supplier, has selected Sequence Design's PowerTheater for precision power calculations at RTL, routinely reducing power consumption by as much as 20 percent according to Kazunori Matsuura, Engineering Group Director, Axell Corporation.

Axell recently taped out a complex graphic chip comprising multi-million gate devices with PowerTheater.

"With a very precise measurement of power at RTL we could determine power budgets and make packaging decisions early in the design cycle which reduces costs significantly," Matsuura said.  "In addition to its outstanding accuracy at RT level, PowerTheater was also quite easy to use. Designers could visualize and resolve power-related problems quickly."

PowerTheater is the industry's first RTL power analysis and management solution with the singular ability to accurately estimate and reduce power at RTL and support power management techniques such as voltage islands, mixed voltage threshold, power gating, and clock gating.

PowerTheater recently added support for the Si2 CPF standard along with the following new features:

* Control all aspects of running PowerTheater through a single Tcl-based command file.

* Identify high power windows utilizing comprehensive simulations from hardware accelerators.

* Compute full-chip, gate-level power efficiently using RTL simulations.

* Prevent voltage-drop related test and functional failures by automatically identifying critical vectors from multiple simulations.

PowerTheater-Explorer is an innovative option that adds state-of-the art power visualization and debug capabilities for fast, interactive power reduction. A new SmartSource Viewer allows designers to determine hot spots in the design, to visualize, debug and interactively determine ways to reduce a design's power.

The hierarchical RTL power tree display shows hot spots that can be cross-probed to schematics, showing connectivity and indicating how activity is moving through the design and how instances impact one another. These results can be displayed and analyzed at RTL, gate, or mixed levels of abstraction. SmartSource also provides a dedicated view of the clock tree for fast isolation and optimization.