SAN FRANCISCO, USA: A year after shifting the objective of its lithography program to the 32nm half pitch node, IMEC has reported progress on high-index 193nm immersion lithography, double-patterning schemes for 193nm water-based immersion lithography and extreme UV (EUV) lithography.

Luc Van den hove, executive vice president and COO at IMEC, said: "Over the last year, we have made significant progress in the three litho approaches we are investigating within our advanced lithography program. Driven by the needs to quickly develop 32nm processes for memory applications and based on the promising results, we are quite confident that double patterning will be taken up as an intermediate solution for 32nm half pitch before a single exposure solution is ready for production."

High-index 193nm immersion lithography
IMEC and ASML will extend their strategic partnership on immersion lithography with the installation of ASML's XT:1900i (1.35 NA (numerical aperture)) at IMEC's 300mm clean room in 2008. Currently, IMEC's immersion lithography research is carried out on ASML's XT:1700i (1.2 NA). The ultimate target of high-index immersion lithography is to drive the NA up to 1.55-1.60, which will enable to extend 193nm immersion lithography to the 32nm half pitch node. In the field of high-index fluids, several fluids have been investigated and at least one fluid seems to meet most criteria in terms of lithographic and interaction properties.

Double patterning schemes for 193nm water-based immersion lithography
After very early feasibility demonstration of 32nm half pitch patterning using double patterning, IMEC currently investigates critical challenges such as mask design split, more cost-effective processes, and critical dimension (CD) and overlay control. IMEC researches double patterning as an intermediate solution for 32nm before a single exposure alternative is ready for production Using an in-house developed accurate CDU model, IMEC has demonstrated the potential capability to achieve sub-3nm CDU, which is the requirement for 32nm half pitch CD control. Using this model, simulations have shown that a more uniform wafer CD distribution can be obtained by minimizing the mean difference between the CD populations, by compensating for intra-field CD variation and by optimizing the etch variation across the wafer.

IMEC also researches techniques to split full chip designs in an automated way, which will be required when the double patterning technique is to be used in a production environment. To this end, design split rules need to be developed that lead to an optimum cutting and stitching strategy, where a trade-off needs to be found between scripting complexity and design regularity.

IMEC is currently running a systematic investigation of the constraints to ensure designs to be split-compliant. Work is done in collaboration with leading EDA vendors that develop the software. It also develops cost-effective process flows for double patterning. A resist freezing process in which the intermediate etch step is skipped by treating the first litho pattern such that the second resist layer can be coated and patterned on top of it, shows promising results. More and more samples developed by various resist suppliers are coming available and are then tested for feasibility and readiness at IMEC.

Extreme UV
EUV lithography is the third lithography option being explored at IMEC for the 32nm half pitch. This is the only lithography option with a clear extendibility towards 22nm and possibly beyond. IMEC entered the last phase in the integration of the ASML alpha demo tool with Sn source. The optics is currently being fine-tuned for high resolution imaging and acceptance testing. IMEC's research program has so far been focusing on:
interference exposures at the Paul Scherrer Institute in Switzerland for resist preparation, design and reticle tape out, and EUV simulations to prepare all the projects.

Besides these three different approaches, more and more effort is also spent to identify the limitations of today's chemically amplified resists in pushing them down to 30nm feature sizes and below, with good line-edge roughness and high sensitivity. Alternative resist chemistries are being tested to overcome these limitations.