SAN JOSE, USA: The Fabless Semiconductor Association (FSA), the global voice of the fabless business model, has released its Hard Intellectual Property (IP) Quality Risk Assessment Tool version 3.0.

The Tool, the first deliverable in FSA's IPecosystem Tool Suite, collects information about an IP vendor, its design methodology and the IP family under evaluation to develop a risk assessment profile across seven criteria: IP design, integration, verification, process technology, product documentation, reliability and test.

The latest version includes several enhancements that improve ease-of-use and increase communication for integrators and vendors, as well as foundries, including:

Custom Questionnaire: A new custom questionnaire allows vendors to add questions pertaining to specific IP.  The integrator completes those questions and can weight specific factors.  This benefit facilitates vendors communicating a message to an integrator about a specific IP family.

Answer Verification: A filter added to the Hard IP summary page allows an answer to be verified. This feature allows vendors and integrators with long-term relationships to add a yes/no confidence level, reflected in a risk profile.

Feedback Button: The feedback loop button has been enhanced so integrators can provide feedback directly to the vendor, aiding the vendor in evaluating additional improvements to its IP.

ChipEstimate.com Collaboration: Vendors now have an option to upload their Tool "risk profiles" to Chip Estimate's IP portal.  In addition, Chip Estimate users may request a vendor's risk profiles or request that a vendor complete the Tool for their IP or family of IP within their portfolio.

IP integrators, from fabless, integrated device manufacturer (IDM) and design companies, that purchase third-party IP or evaluate internal IP for reuse, gain increased intelligence utilizing the Tool.

"The latest version of this tool helps to expedite SoC design by setting a quality risk profile for IP," said Craig Hunter, Power Embedded Core project manager for Freescale Semiconductor. "Establishing a common benchmark for interchangeable IP can help boost the overall quality of SoC designs."

The Tool is now available complimentary to the industry.