Challenge and promise of low-power IC design

Low-power IC Design

Challenge and promise of low-power IC design

Power management is becoming an important aspect for almost all categories of design

Dr. Anand Anandkumar

Wednesday, October 01, 2008

BANGALORE, INDIA: In the past, due to a high degree of process complexity and the exorbitant costs involved, low-power integrated circuit (IC) design and applications technologies were used only in applications where very low power dissipation was absolutely essential, such as wrist watches, pocket calculators, pacemakers, and some integrated sensors.

Dr. Anand Anandkumar, VP Sales, Globalization and MD, Magma Design Automation India

Dr. Anand Anandkumar, VP Sales, Globalization and MD, Magma Design Automation India

Today, with the dramatic increase in power requirements, power management is becoming an important aspect for almost all categories of design. The popularity of cell phones, MP3 players, PDAs and other handheld devices has made extended battery life a major selling point for portable systems. Increasing awareness of global warming and green technology is also driving the demand for low-power designs.

The rising energy costs and geopolitical forces are causing everyone to rethink how they consume power. As a result, semiconductor and EDA vendors are developing new methodologies and tools that allow them squeeze as much as they can from tightening power budgets.

Enabling power savings
The opportunity to save power is at maximum in the early stages of IC design. To enable this power savings, EDA vendors are supporting a balanced approach to power optimization that spans the entire RTL-to-GDS flow, and provides a higher degree of automation. Traditional design techniques, such as clock gating and clock tree synthesis, are being tweaked to ensure that high-power areas in a design are identified and that steps to reduce power consumption are automated.

EDA vendors are taking steps to ensure that these design tools and techniques fit into existing flows and do not adversely affect timing, performance and area. Since power consumption spans almost all structures in a chip, only broad-based EDA vendors can offer solutions that analyze and optimize power in everything from clock trees to I/Os.

However, EDA vendors with a broad range of solutions, as well as smaller point-tool providers, are working to automate the process while still giving engineers ultimate control. For every watt saved at the chip level, at least three times that amount is saved in the overall system.

There are a variety of low-power design techniques that engineers are reinventing. They all have one thing in common, namely exhaustive analysis of where power is being consumed. This allows designers to make trade-offs to save power where ever they can. For example, if a person is talking on a cell phone, it’s unlikely that they’ll need to use the camera function or even a keypad.

Holistic approach of designers
Selectively shutting power down to an unused block is important, but designers have to be careful when choosing which blocks to shut down and when. Powering up a block and its associated clock tree also consumes power, so needlessly shutting down blocks that are used often can actually consume more power than if they were left on for a period of time. Designers are taking a holistic approach when analyzing their designs for power savings.

In addition to power, area, performance and yield considerations, designers are using an integrated approach from the architectural level all the way down to placed gates. This lets the designer make 'what-if' trade-offs throughout the design cycle, which can save valuable time by avoiding the need to make changes right before fabrication when such changes are more time consuming, expensive and inefficient.

As power-saving techniques become more widely used and sophisticated, the amount of power saved is also increasing. With today’s techniques, most of which happen at the RTL, engineers are getting power savings in 10 percent increments, usually topping out at 40 or 50 percent.

At the system level, the power savings can be even larger. Implementing low-power techniques requires tool support, an awareness of the system constraints, and a voltage-aware verification methodology. Use of the open, industry-standard Unified Power Format (UPF) for capturing design power intent is highly recommended. UPF allows power intent to be captured as part of the design semantics, separately from the functional RTL.

In addition to the trend in mobile and handheld devices, reducing power consumption in workplace computing and communications is gaining popularity, especially with increasing global environmental awareness. In fact, power has emerged as one of the most important design and performance parameters for ICs.

Today, IC designers are challenged to design circuits with low-power consumption, without severely compromising the circuits' performance. The good news is that EDA vendors are working to automate the analysis and repair process from the highest architectural level down to placed gates and allowing engineers to analyze a design at every phase of the design cycle to conserve power.

There is lot more demand for low power ICs, but there are also a lot more effective solutions available, and more to come. This advancement is just what is needed to maintain the pace of Moore's Law.

The author of the article is VP Sales, Globalization and MD, Magma Design Automation India, a leading provider of chip design software. The author can be reached at ananda@magma-da.com

©CIOL Bureau

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