NXP intros bidirectional voltage I2C-bus translation buffer

By : |August 13, 2013 0

EINDHOVEN, THE NETHERLANDS & SAN JOSE, USA: NXP Semiconductors N.V. announced the availability of the PCA9617A Fast-mode Plus (Fm+) I²C-bus buffer, designed for emerging server applications that use DDR4 SDRAM memory.

This breakthrough voltage-translating bus buffer allows engineers to design next-generation server systems using new DDR4 technology with the I²C-bus operating at up to 1 MHz, and voltage level translation of 0.8V on the CPU side to 2.5V on the SDRAM module side. NXP continues to drive innovation on the I²C-bus, a widely adopted bus system management and control technology used in virtually all computing and enterprise equipment applications. The PCA9617A is the first Fm+ device specifically designed for servers. It operates up to 1 MHz with normal Fast-mode drive to allow operation on more heavily capacitive loaded buses, but is backward-compatible to Fast-mode and Standard-mode speeds.

The PCA9617A is a CMOS integrated circuit that provides voltage level shifting between 0.8V and 2.5V supply voltages for Fast-mode plus I²C-bus or SMBus applications. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, one bus, split into two sections of 550 pF (max) at 1 MHz.


Using the PCA9617A enables the system designer to buffer the load capacitance of the bus, and provide voltage level translation. The SDA and SCL pins are overvoltage tolerant and are high impedance when the PCA9617A is unpowered. Evaluation samples and demo boards are available immediately.

The PCA9617A is available in TSSOP8 (MSOP8) “DP” and smaller leadless HWSON8 “TP” packages.

The PCA9617ADP and PCA9617ATP are both are in volume production priced at $0.54 in 10K quantities. Evaluation samples and demo boards are available immediately.

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