Lighting up ‘dark silicon’

LONDON, UK: Mike Muller, CTO of ARM, is scheduled to deliver the keynote address at EE Times’ Designing with ARM virtual conference on March 25, 2010.

According to Mike Muller, despite process scaling down to 11-nm, fixed-power budgets may soon make it impossible to use all the available transistors on a chip.

Without fresh innovations, Muller says, designers could, at some point, find themselves in an era of “dark silicon,” able to build dense devices that they cannot afford to power.

Mike Muller substantiates his argument with the following numbers: Compared to a 45-nm die, 22-nm will enable a 4X die shrink; and 11-nm will enable a 16X die shrink. Taking 45 nm as the reference point, the peak frequency at 22 nm can increase to 1.6X, and at 11 nm, to 2.4X.

In his keynote address, Mike Muller will discuss in detail tactics and strategies “to light up” what would otherwise be “dark silicon.”

According to Mike Muller, silicon on insulator (SoI) will have a prominent role. The SoI chips go a long way in addressing the leakage problem at smaller geometries.

While energy-efficient, robust high-density memories will facilitate reduced operating and retention voltages, 3D silicon integration (3D ICs) will enable high levels of energy efficiency and improvement in performance.