LatticeECP3 FPGA now compliant with PCIe 2.0

BANGALORE, INDIA: Lattice Semiconductor announced on Tuesday that its LatticeECP3 Field-Programmable Gate Array (FPGA) family was compliant with the PCI Express 2.0 specification at 2.5Gbps.

According to a press release from the company, the LatticeECP3 FPGA and its PCI Express (PCIe) IP Core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations at a recent PCI-SIG workshop, ensuring that Lattice's solution is interoperable with existing PCIe 2.0 supported systems.

The company claimed that it would enable cost and power reduction with higher reliability for 2.5Gbps PCIe v2.0 systems for communications, multimedia, server and mobile platforms, and would add to the range of design solutions from Lattice and its IP partners that support the widely-adopted serial interconnect standard.

The PCIe v2.0 specification allows operation at a lower speed (2.5Gbps), but the loop bandwidth characteristics are different and more rigorous than for PCIe v1.1. At the same time, the solution is designed to allow customers, who do not need the PCIe link, to operate at 5Gbps, but who care about PCIe v2.0 compliance, to use a low-cost FPGA in PCIe v2.0 compliant systems.

Lattice has worked with Trellisys Ltd towards providing a robust and cost-effective PCIe Bus Functional Model (BFM) for Lattice's PCI Express x1 and x4 IP Cores. The Trellisys PCIe BFM concentrates on the transaction layer and this approach assumes that physical and data link layers, which are completely encapsulated in the Lattice PCIe IP Cores, have already been verified by Lattice, added the release.

“The Trellisys PCI Express BFM brings the verification investment back in line with the FPGA development flow, while still maintaining an effective verification concept,” said Charles Gardiner, director, Trellisys.

“Since PCI Express 2.0 has more rigorous testing requirements compared to PCI Express 1.1, successfully testing against the PCI Express 2.0 specification provides more robust operation with other PCI Express 2.0 compliant devices,” he added.

The release stated that the Trellisys PCIe BFM supported both Verilog and VHDL and has been verified on both the Aldec Active-HDL and Riviera-PRO simulators. It is delivered as precompiled code but provides the user with a powerful procedural library, on which an advanced verification suite can be based.

“This collaboration provides validation IP that will enable users to reduce design complexity and shrink the time to market window for their PCI Express designs,” said Shakeel Peera, director of marketing, Silicon and Solutions at Lattice.