Lattice breaks rules with ECP5 FPGA family

HILLSBORO, USA: Lattice Semiconductor Corp. announced its ECP5 family for small-cell, microserver, broadband access, industrial video and other high-volume applications where the lowest-possible cost, lowest-possible-power, and smallest-possible form-factor are crucial.

The ECP5 Family ‘breaks the rules' of conventional FPGA approaches to deliver a SERDES-based solution for designers to rapidly add features and functions to complement those delivered by ASICs and ASSPs, reducing development risk and quickly overcoming time-to-market challenges.

Lattice optimized the ECP5 family's architecture with the goal of delivering the best value below 100k LUTs for performing critical functions as a companion chip to ASICs and ASSPs. Achieving 40% lower cost than competing solutions, optimizations include small LUT4 based logic slices with enhanced routing architecture, dual-channel SERDES to save silicon real estate, and enhanced DSP blocks for up to 4x resource improvements.

"The ECP5 family breaks the rule that FPGAs should be the highest density, power hungry and expensive," said Lattice Semiconductor president and CEO Darin Billerbeck.

"Lattice's newest family serves to provide customers with an ASIC/ASSP companion chip as the quickest path for removing development obstacles at a time when mobility and mobile infrastructure are driving the need for small size and low power in practically every facet of the electronics industry."

The global deployment of next generation telecommunications systems is driving small-cells into high-volume, access and networking equipment is becoming commoditized and video display technologies continue to

advance.

For each of these applications, FPGA capabilities in a tiny, low-cost form-factor burning just milli watts of power can eliminate many roadblocks for pursuing opportunities that would otherwise be ruled out due to ASIC development costs and schedules, or ASSP inflexibility and availability.