Faraday increases performance of its largest SoC

By : |November 19, 2013 0

SAN JOSE, USA: Cadence Design Systems Inc, a leader in global electronic design automation, announced that Faraday Technology Corp, based in Hsinchu, Taiwan, deployed a full Cadence tool flow to create its largest SoC, a 300 million gate design for a 4G base station.

By using Cadence Encounter digital design tools in Faraday’s hierarchical flow, the design team completed this complex SoC, from data-in to tapeout, in just seven months.

Faraday successfully reduced the time for each prototyping run of this SoC design from two weeks to 3-5 days by leveraging EDI system, including GigaOpt multithreaded optimization and advanced analysis, Encounter Conformal EC for hierarchical EC compare methodology, and integrated signoff tools for RC extraction and timing analysis.


Additional Cadence products used include incisive enterprise simulator, VIP, encounter power system, Allegro package designer and Allegro sigrity signal and power integrity solutions.

“This SoC was the biggest project we’ve undertaken, and is the most complex one ever in Taiwan, so we compiled the best tool set we could to ensure success, in performance, quality and in time to market;” said Jason Hung, RD VP of Faraday. “Cadence’s wide array of digital implementation and verification products plus the level of support we received helped us achieve all our goals.”

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