DesignWare IP simplifies transition to PCI Express

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of the DesignWare LE IP for PCI Express (PCIe) optimized for ASIC and FPGA designs that utilize a single lane (x1) PCI Express endpoint interface.

The DesignWare LE IP for PCIe is a cost-effective solution that provides innovative ease-of-use features to simplify the complexities of transitioning to PCI Express for applications requiring a single lane, such as existing PCI/PCI-X designs, ExpressCards, Ethernet controllers, SATA controllers and wireless hubs.

The new DesignWare LE endpoint digital controller IP for PCIe provides a simplified feature set that enables designers to benefit from a 20 percent area reduction in their ASIC or FPGA implementations while maintaining the same architecture and interfaces as Synopsys' complete DesignWare IP for PCIe solution. By maintaining interface compatibility, designers can upgrade to a full-featured version when future designs require additional functionality.

The silicon-proven DesignWare LE IP is a part of Synopsys' complete PCI Express IP portfolio and has successfully passed the PCI Express compliance testing at the PCI-SIG interoperability workshops.

The DesignWare LE IP utilizes several innovative ease-of-use features to lower the integration time and cost of incorporating PCI Express IP into a design. The DesignWare LE IP automatically connects the PCI Express digital controller and PHY together.

During implementation, the DesignWare LE IP automatically optimizes the parameters across the PIPE interface and synthesizes the complete PCI Express interface. In addition, the new IP includes a reference design that helps designers quickly integrate the PCI Express interface, while providing a starting point for the assembly and verification of their chip design. The DesignWare LE IP for PCI Express is available immediately.