DARPA funds to foster STT-RAM chips

SAN JOSE, INDIA: Defense Advanced Research Projects Agency (Darpa) will  grant a $8.6 million fund to Grandis Inc for developing spin-transfer torque random access memory (STT-RAM) chips during the second phase of the research project. STT-RAM is a next-generation MRAM technology.

The first phase of the project, which began in 2008, is supported by an award amount of $6.0 million slated for two years. The system is realized by a alliance between Grandis, the Universities of Virginia and Alabama, and the College of William and Mary.

The other services to the program were being given by the National Institute of Standards and Technology and the Naval Research Laboratory. The program encloses STT-RAM materials and processes, as well as STT-RAM architecture and circuit blocks. The second phase includes testing and verification of STT-RAM integrated memory arrays.

According to Farhad Tabrizi, CEO and president of Grandis (Milpitas,California),STT-RAM has a huge potential as the only non-volatile Random Access memory which scales beyond 10-nm.It is the only technology that can possess the ability to reinstate the existing DRAMs. It can replenish embedded SRAM and flash at 45-nm, DRAM at 32-nm, and can supercede NAND, he said.