BANGALORE: Synplicity Inc. and Xilinx Inc. today announced the formation of joint Ultra High-Capacity Timing Closure Task Force.
Engineering teams from both companies will collaborate to define and implement new design flows that maximize the quality of results and design productivity of ultra high-density designs with next-generation 65-nanometer (nm) FPGAs.
The industry's first 65-nm Virtex-5 FPGA family introduced by Xilinx, includes devices with up to 330,000 logic cells, 10-Mb on-chip memory, 1,200 I/Os and a host of additional hardened intellectual property (IP) blocks on the new Virtex-5 LX Platform.
Synplicity and Xilinx will build upon their existing support of these 65-nm devices to develop next-generation design automation solutions that enable system designers to take full advantage of their capacity and performance while achieving rapid timing closure.
Bruce Talley, vice president, Design Software Division at Xilinx, said, “The Synplicity team has a great deal of experience and track record of innovation when it comes to high performance, complex FPGA design with products like Synplify Pro and Synplify Premier physical synthesis. This joint task force provides an opportunity to more quickly leverage engineering expertise and creativity across our development organizations.”
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