MOUNTAIN VIEW, CALIF:. Synopsys, Inc. and UMC announced the release of a 65-nanometer (nm) hierarchical, multi-voltage RTL-to-GDSII reference design flow.

The flow is based on Synopsys' Galaxy Design Platform and features the IC Compiler place-and-route solution and the Design Compiler Ultra topographical synthesis solution for comprehensive design implementation support.

Key features of the reference flow include support for power management with multi-voltage design and power gating, as well as design-for-manufacturing (DFM) capabilities with the addition of critical area analysis (CAA).

Power gating reduces standby leakage by shutting off areas of the chip that are not in use for a particular function. The CAA capability, provided in IC Compiler, determines the likelihood of random particle defects affecting the overall design.

Engineers can use this capability to identify design structures that have a higher probability of yield loss and correct them before manufacturing.

This combination of tools and flow better equips engineers to reduce power consumption and improve yield, both significant 65-nm design challenges.

The reference flow also utilizes Synopsys' Design Compiler Ultra topographical synthesis engine, enabling engineers to accurately predict chip performance results such as timing, area, testability and power consumption during logic synthesis.