Cadence unveils verification kit for wireless consumer SoC design

Cadence unveils verification kit for wireless, consumer SoC design

Provides methodology that extends from block-level verification to chip- and system- level advanced verification

Tuesday, August 28, 2007

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SAN JOSE, USA: Cadence Design Systems, has unveiled verification kit for wireless and consumer system-on-chip (SoC) design, enabling engineers to adopt advanced verification techniques with reduced risk and deployment effort and meet time-to-market requirements. The Cadence SoC Functional Verification Kit provides methodology that extends from block-level verification to chip- and system- level advanced verification and includes automated methodologies for implementation and management. The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries—all proven on a wireless segment representative design and delivered through applicability consulting.

"The Cadence SoC Functional Verification Kit is just what is needed for today's feature rich SOC designs," said Chang-Soo Kim, CTO at Kairos Logic Co., Ltd. "In working with the kit, we can see the tremendous time savings the kit provides with its pre-build verification environment, IP and working examples. We believe the delivery mechanism using verification experts is a fantastic way to ensure risk reduction through deep comprehension of the Incisive Plan to Closure coverage driven methodology."

The new kit from Cadence addresses key challenges engineers face when designing and verifying SoC designs: ensuring comprehensive verification of the design, enabling re-use, managing low-power modes typical in today's SoCs, ensuring hardware-dependent software coverage, and accomplishing the verification within very stringent time-to-market timelines.

"Functional verification of SoC designs is one of the most difficult and time-consuming challenges our semiconductor and systems partners face today," said Graham Budd, executive vice president and general manager of the Processor Division at ARM. "Through the kits initiative and ARM collaboration, the Cadence SoC Functional Verification Kit directly addresses these challenges and helps our mutual customers get their products to market more efficiently."

The applicability consulting included with the kit provides complete and interactive guidance for performing predictable and repeatable verification of blocks, clusters, full chips, and SoCs, and enables design teams to quickly and easily adopt the Cadence Incisive® Plan-to-Closure Methodology.

The SoC Functional Verification Kit includes design and verification IP from Cadence and third parties, including an accurate high-speed model of the ARM968E-S processor, AMBA PrimeCell IP® including interconnect and peripherals, and the ARM RealView Development Suite debugger, USB 2.0 from ChipIdea, and 802.11 from WiPro. The kit includes three main flows: architectural, RTL block to chip, and system-level. Users can implement the entire kit as an integrated flow, or may select flows individually. Also included are 13 workshop modules and over 40 hands-on labs which engineers can use to incrementally improve their verification productivity.

"With today's wireless and consumer chip designs becoming increasingly complex, design teams are under growing pressure to apply more effective verification methods and technology," said Moshe Gavrielov, executive vice president and general manager, Cadence Verification Division. "The SoC Functional Verification Kit delivers a solution spanning the full verification process to ease adoption of advanced verification capabilities for design and verification teams."

The Cadence Incisive Plan-to-Closure Methodology will support the Open Verification Methodology or OVM in Q4 this year. The OVM is based on Cadence's Incisive Plan-to-Closure URM module and Mentor's Advanced Verification Methodology module.

The new SoC Functional Verification Kit will be featured at the CDNLive! Silicon Valley technical conference, scheduled for Sept. 10 to 12, in San Jose, Calif. More information on the conference can be found at http://www.cadence.com/cdnlive/na.

Cadence Kits
Cadence kits enable IC designers to accelerate technology-specific product development and address design challenges in EDA technology segments such as analog mixed signal, silicon-in-package (SiP), coverage-driven functional verification, and radio frequency integrated circuit (RFIC). By using Cadence kits, customers can focus more of their design resources on design differentiation rather than developing design infrastructure.
©CIOL Bureau

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