BANGALORE, INDIA: According to ARM's director of engineering, Jayanta Lahiri, designers today are conscious about yield. The key is to have a good strategy in place for DFY (design for yield). Here, he provides tips for improving yield, in an exclusive with Pradeep Chakraborty, executive editor, CIOL. Excerpts:

CIOL: Are designers conscious of yield? If not, why and what should they do to improve?

Jayanta Lahiri: Yes, the designers are conscious about yield. The issue is having a good methodology or strategy in doing DFY (design for yield).

Sometimes, DFY leads to increase in area which is counter-productive for yield. What really matters is net good die per wafer. The yield and average selling price (ASP) combine to give a profit of the product. In a nutshell, DFY can be defined as: "Things that can be done to increase amount of working silicon."

There are not many good tools available to measure what is the percentage impact on yield if the design for manufacturability (DFM) guidelines are met. To get a feel of the DFY, designers should start thinking of yield right at the time developing the cell library. The layouts of the library cell should be made DFM aware without increasing the cell area.

CIOL: Is the yield accurately mapping into the technical parameters that would ultimately lead to higher yield percentage?

JL: The mapping between yield and key process parameters is a complex relation. Relative ranking of issues: random, systemic, and parametric.  Random (particle defects) and parametric (transistor models) are completely controlled by the foundry. While systematic can be controlled by the IP vendor or the SOC companies by making the design more robust.

CIOL: What are the challenges and how can those be overcome?

JL: As the feature size is reducing, it is becoming extremely difficult to map all the process parameters correctly to the model parameters to forecast the yield. Failure rates and data will be inherently biased towards critical circuits.

Try to space out your critical circuits. Circuits with more slack have more inherent fault tolerance try to have slack in timing if it is not in the critical path for speed.

Some examples of  good DFY practices will be non-minimum layout design rules (line spacing) wherever possible, Mask fixes (optical proximity correction), Design margining, etc.

CIOL: What is ARM doing in this area?
JL: The things that ARM is doing are as follows:

* Follow foundry guidelines and establish good layout practices;
* Incorporate design margin and variability tolerant design;
* Build yield optimized cells (via doubling, extra spacing).

The things where ARM needs help from partners or foundries to achieve good yield are as follows:

* Anything requiring fab process details (OPC, metal etch, etc.)
* Anything requiring huge numbers of silicon measurements -variability statistics, modified SPICE models etc.