PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM demonstrator built using 32nm design rules.

PULLNANO is a collective effort of 38 European partner organizations, including leading chip manufacturers, industry-orientated research institutions, universities and SMEs. Its aim is to develop advanced knowledge that will enable European chip manufacturers to maintain their strong presence in the worldwide microelectronics industry from 2010, when the 32nm generation of CMOS technology is expected to be commercially available.

SRAM is required in most complex SoC devices that are built with leading-edge CMOS technologies and the demonstration of a functional SRAM is therefore, an important milestone. The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

The transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI), coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is said to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together.

PULLNANO is ahead of schedule in reaching this first milestone and also expects to demonstrate an even smaller cell before the end of the year. At the IEEE International Interconnect Technology Conference, held in June 2007 in San Francisco, PULLNANO partners also reported results relating to the Back-End Of the Line (BEOL) part of the PULLNANO project.