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CircuitSutra intros SystemC model of AMBA AXI4 for HLS based design flow

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Sharath Kumar
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BANGALORE, INDIA: As the SoC complexity keeps on increasing and as RTL code size is becoming huge, designing or reusing IPs, verifying them, optimizing them for constraints like area, power, performance while meeting time to market targets is becoming difficult. That leads to serious discussions about moving up one abstraction level above RTL i.e. to High Level Synthesis (HLS)

CircuitSutra describes how it used the SystemC based HLS design flow to design the AXI communication protocol, and the benefits that we realized. We developed the re-usable master & slave sockets that can be used by the designers to design the IP modules compliant with AXI protocol. RTL is generated by synthesizing the SystemC models using Cadence Cynthesizer tool.

One of the major roadblocks in the adoption of HLS based design flow is the non-availability of re-usable models. The AXI model explained in this presentation is part of the High Level Synthesis - Quick Start Package (HLS-QSP) from CircuitSutra, a library of basic models and modeling infrastructure that enables the customers to quick start a SoC design using HLS methodology.

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