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Novocell expands its Smartbit family, intros NVM IP Tape

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Novocell has launched the successful tape out of the firm’s Smartbit-based non-volatile memory (NVM) in a 32nm SOI process at IBM’s foundry in cooperation with the Trusted Access Program Office (TAPO)

CALIFORNIA, USA: Novocell Semiconductor, a one-time programmable (OTP) antifuse non-volatile memory (NVM) provider has launched the successful tape out of the firm’s Smartbit-based non-volatile memory (NVM) in a 32nm SOI process at IBM’s foundry in cooperation with the Trusted Access Program Office (TAPO).

Novocell continues their record of industry leadership with this announcement, further extending their Smartbit-based family of antifuse OTP to the 32nm advanced node.

Walt Novosel, President of Novocell, said, ''We are pleased to announce this latest demonstration of our long term tradition of innovation and leadership by advancing our innovative product offerings to this advanced node to serve current and future customers' needs. Novocell continues to work closely with customers to develop the most reliable NVM in our category and to offer our patented Smartbit OTP NVM technology at the most cutting edge technologies.''

The company claims that, the Smartbit-based NVM IP products avoid the limitations of traditional embedded NVM technology by utilizing the patented design and dynamic programming and monitoring process of the Novocell Smartbit bit cell, ensuring that 100 per cent of customers' embedded bit cells are fully programmed.

The result is Novocell's unmatched 100 per cent yield and unparalleled reliability, guaranteeing customers that their data is fully programmed initially, and will remain so for an industry-leading 30 years or more.

Novocell IP based on the Smartbit bit cell utilizes standard CMOS manufacturing processes, without secondary masks or additional fabrication processes. Novocell non-volatile memory IP has been designed to provide the most foundry and process-independent IP solutions available, and continues to scale to meet node and process complexity challenges as SoC firms migrate chip designs to advanced, low power nodes such as 32nm and beyond.

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