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Synopsys' silicon-proven DesignWare USB 3.0 and USB 2.0 femtoPHY IP cut area by 50 percent

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Small footprint PHYs on 14/16-nm FinFET and 28-nm processes reduce silicon cost

MOUNTAIN VIEW, USA: Synopsys Inc. has reduced the area of USB PHY implementations by up to 50 percent with the new DesignWare USB femtoPHY IP, minimizing USB PHY silicon footprint and cost for designs in 28-nanometer (nm) and 14/16-nm FinFET processes.

The DesignWare USB femtoPHYs have shown robust performance in 28-nm and 14-nm FinFET silicon, enabling designers to implement the IP in advanced process technologies and reduce system-on-chip (SoC) design risk.

The DesignWare USB 3.0 and USB 2.0 femtoPHYs are optimized for extremely small area, meeting the stringent requirements of mobile devices such as smartphones and tablets, high-volume consumer applications such as digital TVs, storage, and networking applications.

The DesignWare USB 3.0 and USB 2.0 femtoPHY IP (DWC SS USB femtoPHY Samsung 14nm FinFET and DWC HS USB femtoPHY Samsung 14nm FinFET) have passed USB-IF compliance testing in a third-party lab. The DesignWare USB femtoPHYs meet or exceed the USB-IF standard specifications, including 5V tolerance and 3.3V signaling, offering robust performance that benefit system configurations operating across all corners of the specification.

The DesignWare USB femtoPHYs support complete USB implementations to provide system architects with a wide range of SoC design options. Both DesignWare USB 3.0 and USB 2.0 femtoPHYs support Hi-Speed, Full-Speed and Low-Speed operation as well as Host, Device and On-the-Go configurations, and the DesignWare USB 3.0 femtoPHY also supports SuperSpeed USB (USB 3.0).

"Building on our long history of successfully using DesignWare USB IP, we have achieved first-pass silicon success with the high-quality DesignWare USB 3.0 and USB 2.0 femtoPHY IP," said Dr. Shawn Han, VP of foundry marketing at Samsung Electronics.

"The DesignWare USB femtoPHY IP, manufactured in the Samsung Foundry, is the first 14-nm FinFET silicon to pass USB-IF certification. Integrating a significantly smaller PHY improves the competitiveness of our customers' SoCs and simplifies the addition of USB connectivity. Synopsys' DesignWare femtoPHYs meet high-volume mobile and consumer applications' cost, power, performance and time-to-market requirements, which are critical components for our success in these fast-moving markets."

Synopsys developed the USB 3.0 and USB 2.0 femtoPHY IP to enable designers to select the optimal implementation for their application without sacrificing the features or capabilities required for USB compliance certification. Designs requiring high performance can take advantage of the USB 3.0 femtoPHY's 5.0 Gbps data transfer rates per the SuperSpeed USB (USB 3.0) specification.

Applications requiring lower performance can implement the USB 2.0 femtoPHY's 480 MHz data transfer rates per the Hi-Speed USB (USB 2.0) specification. Both DesignWare USB femtoPHYs minimize the number of pins needed on the SoC periphery to further reduce SoC area and cost. Power down features minimize battery drain when the PHY is inactive, while retaining all PHY states to enable fast, accurate power-on capabilities.

In addition, the DesignWare USB femtoPHYs support the popular USB Battery Charging v1.2 specification and the USB On-The-Go (OTG) v2.0 protocol.

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