Cadence SP&R upgrade speeds design of large chips

BANGALORE: Cadence Design Systems, Inc., supplier of electronic design

products and services, has introduced a broad upgrade to its SP&R

(synthesis/place-and-route) integrated RTL-to-GDSII design solution that enables

designers to produce higher-performance chips in shorter design cycles than ever

before. The new Cadence SP&R technology delivers significantly more powerful

timing and signal integrity optimization, more than twice the performance in

synthesis and routing, and next-generation power planning for large, complex

integrated circuits (ICs).

This release of Cadence SP&R technology includes enhancements to

BuildGates synthesis, Physically Knowledgeable Synthesis (PKS), Silicon

Ensemble, and SoC Encounter place-and-route systems which shorten the time it

takes to design multi-million-gate digital ICs. Cadence SP&R Enhancements

address Deep Sub-Micron Challenges Cadence SP&R has enhanced performance and

features to address the design challenges of sub-0.13-micron process technology:

Physical synthesis and routing performance improvements, Flexible and productive

next-generation power planner, Post-route signal integrity optimization.






Other enhanced features include physically knowledgeable power analysis and
optimization, Advanced datapath optimization integrated in logic and physical

synthesis, Introducing BuildGates Extreme synthesis



and Routing enhancements satisfy requirements for sub-0.13-micron process
technology.






The new release of Cadence SP&R is available immediately for Sun Solaris and
HP's HP-UX UNIX operating systems. One-year US list prices for BuildGates

synthesis, BuildGates Extreme synthesis, and PKS physical



synthesis products start at $20,000, $50,000, and $150,000 respectively. US list
prices for Silicon Ensemble and SoC Encounter start at $400,000 and $695,000.