Cadence on mixed signal design complexities

BANGALORE, INDIA: According to Tom Beckley, senior VP of custom IC and PCB design, Cadence, growing the RF content is a must. Staying connected is a major driver for RF content. Mobility, IoT are driving the network infrastructure growth.

Beckley was speaking at the CDNLive 2013 event in Bangalore. He added, “We are seeing the early stage of mixed signal design. Google’s self-driving cars gather nearly 1GB of sensor data every second.”

Mixed signal complexity is alive and well. There are verification and implementation challenges. Some of the questions asked are: How do I verify digital content in the SoC? How do I verify the mixed signal interconnect? How do I verify integrated flash and SRAM memories? How do I optimize digital pin placement during implementation?

The biggest mixed signal challenges is A/MS verification with 36 percent, as per a Cadence survey.

Beckley added: “Cadence can help optimize your verification methodology – A/MS + fast ADF XL. We introduced schematic model generator about ninemonths ago. It has 160 building blocks. We have 10 major companies using this. For a global A/MS company, the verification reduced three months. The metric driven methodology has been extended.”

According to him, FastSPICE technology will provide better performance. This is the Specter XPS – which allows high speed, high capacity full chip analysis. It is ideal for verification challenges going forward. You can quickly simulate critical paths with Spectre XPS for high capacity, fast performance and smaller footprint. We are 8-30x throughput over the competition. Spectre XPS has now been officially announced. You can also complete A/MS verification in Virtuoso platform.

OpenAccess is a great step forward. There is a common database (OA), common technology file, common constraints manager, low-power flow (CPF fiile). No more LEF/DEF transitions. We are now taking interoperability to the next level. There are parallel analog and digital designs. Virtuoso now supports mixed schematic and text hierarchies.