Cadence launches verification platform

BANGALORE, INDIA: Cadence Design Systems has launched a high-performance verification computing platform called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment.

Palladium XP verification computing platform lets design and verification teams bring up their hardware and software environment faster and shortens embedded systems turn around time.

The solution supports design configurations up to 2 billion gates, delivering performance up to 4MHz and supporting up to 512 users simultaneously. The platform also provides unique system-level solutions, including low-power analysis and metric-driven verification.

The Palladium XP verification computing platform provides developers a high-fidelity representation of their design so they can quickly and confidently locate and fix bugs, resulting in better-quality IP, subsystems, SoCs and system. Design teams can 'hot swap' simulation with acceleration and emulation in a scalable verification environment as needed, which speeds the verification process and enables early access to  testing embedded software and evaluating performance implications of different IP and/or system architectures.