Cadence announces next-gen Quantus QRC extraction solution

SAN JOSE, USA: Cadence Design Systems Inc. has announced Cadence Quantus QRC Extraction Solution, its next-generation tool for RC extraction.

With its massively parallel architecture, Quantus QRC Extraction Solution accelerates design signoff and sets a new standard for performance by delivering up to 5X faster runtime for single and multi-corner extraction versus competing solutions. Additionally, its accuracy and FinFET functionality have been certified at TSMC.

Quantus QRC Extraction Solution leverages the high-accuracy modeling engine from Cadence's previous-generation QRC Extraction product, ensuring direct compatibility and fully certified libraries for all foundries for existing users of QRC Extraction.

The new tool also provides significant enhancements to support FinFET features. It includes the same market-leading custom/analog functionality of QRC Extraction, and supports the same foundry-certified and -qualified "qrctechfiles." In addition, Quantus QRC Extraction Solution is proven to have the tightest correlation to foundry golden data at TSMC versus competing solutions.

Quantus QRC Extraction Solution supports both system-on-chip (SoC) and custom/analog designs and includes a new foundry-certified integrated random-walk field solver called Quantus FS, which is up to 5X faster and provides better throughput versus competing solutions.

An automated incremental extraction capability reduces design closure turnaround time with up to an additional 3X performance improvement with Cadence Encounter Digital Implementation System and Tempus Timing Signoff Solution. In-design signoff methodology has been enhanced in both Encounter and Virtuoso platforms.

"After validating the runtimes of Cadence's Quantus QRC Extraction Solution on benchmark designs, we have determined that it offers significant improvements without compromising signoff accuracy," said Sumbal Rafiq, director of Engineering at AppliedMicro. "Quantus QRC Extraction Solution's ability to perform multi-corner extraction in a single run using foundry-certified accuracy enables notable design implementation time improvements. This is a well integrated solution that complements Cadence's existing Encounter Digital Implementation tool."

"Despite increasing SoC design sizes and interconnect process corners at advanced nodes, Open-Silicon has achieved design closure quickly by using the Quantus QRC Extraction Solution along with its best-in-class design methodologies and tools," said Radhakrishnan Pasirajan, VP of Silicon Engineering at Open-Silicon.

"As a company that consistently achieves first-pass silicon success, Open-Silicon relies on the massive parallelism and accuracy of this tool to achieve significant performance improvement in its designs. Its scaling capability to utilize hundreds of CPUs, allows our designers to quickly navigate through signoff extraction bottlenecks during tapeout."

"Our customers have emphasized that it is imperative for a signoff parasitic extraction tool to provide the highest accuracy with the fastest turnaround time to ensure timely design closure," said Anirudh Devgan, senior VP, Digital & Signoff Group at Cadence.

"Quantus QRC Extraction Solution has been proven to provide best-in-class accuracy for FinFET designs and deliver significantly better performance versus competing solutions."

Quantus QRC Extraction Solution is available now. Following the 2013 releases of Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution, the Quantus QRC Extraction Solution is the third innovation from Cadence leveraging a massively parallel architecture to speed electrical design signoff and closure.