Advertisment

ATopTech’s Aprisa and Apogee physical implementation tools certified by TSMC for V1.0 16nm FinFET process

author-image
Harmeet
New Update

SANTA CLARA, USA: Aprisa and Apogee, ATopTech's place and route solutions, have been certified for the version 1.0 Design Rule Manual (DRM) of TSMC's 16nm FinFET process.

Advertisment

ATopTech, a leader in next generation physical design solutions, continued their ongoing collaboration with TSMC to optimize ATopTech physical implementation tools to support advanced designs in TSMC 16nm FinFET (16FF). The rigorous certification process ensures that ATopTech tools deliver satisfactory quality of results, including design correctness, routability, timing, power, area and manufacturability for designs in 16FF.

Aprisa and Apogee also passed TSMC's Integrated Tool Certification, where all 16FF design rules and methodologies were validated within the ARM Cortex A15 quad-core processor design hardening flow.

This certification includes all sign-off checks, including DRC/ LVS (design rule checking/ layout versus schematic), IR/ EM (voltage drop and electro-migration check), MVRC (multi-voltage rule check) and formal verification. Customers can request the Aprisa/Apogee Technology File for 16FF directly from TSMC for immediate 16nm design starts.

semicon