ARM announces 40nm G physical IP platform

CAMBRIDGE, UK: ARM has announced the availability of  the industry’s most comprehensive IP platform for TSMC’s 40nm G manufacturing process. This latest silicon-validated physical IP from ARM enables cost-effective development of performance driven consumer devices requiring advanced functionality without increasing power consumption.

Created for developers looking to advance their designs using the 40nm process, the platform enables higher levels of technology innovation while maintaining power budgets in performance driven consumer devices including disc drives, set-top boxes,  mobile computing devices, networking applications, high-definition televisions, and graphic processors.

The ARM platform offers a high degree of flexibility through the multi channel Logic libraries, which include high-performance and high-density Standard Cell libraries, Power Management Kit and ECO Kit library extensions aimed at addressing the leakage challenges of sub-micron designs. All multi channel length libraries are footprint compatible, enabling effortless cell swapping within standard design flows. This enables significant power and cost savings by replacing or complementing the HVt, RVt or LVt implant layers with long channel length devices providing better performance, lower leakage and reduced manufacturing costs.

In addition, the platform includes embedded memory compilers and interface IP to meet a wide range of performance, power and area requirements. The  memory compilers are optimized to deliver the highest SoC performance with the ability to reduce die size while utilizing advanced power management technology to minimize the overall power consumption; resulting in lower die and packaging costs.

Advanced power management is an integral part of the ARM memory architecture offering significant reductions in both dynamic and leakage power in SoC designs. High density memories coupled with ARM’s innovative high speed architecture and multiple processor-specific low power management modes enables superior ARM CPU implementation, unavailable in non-processor optimized solutions.

ARM 40nm Interface IP provides the SoC designer with a comprehensive set of General Purpose I/Os, Speciality I/Os and DDR Interface Macros.  Designed with advanced programmability, the Interface IP enables high degree of flexibility connecting the ARM CPU to the outside world for a wide range of SoC applications.

This Interface IP incorporates several power and leakage saving modes that can be dynamically controlled to further optimize overall SoC power and enable better granularity on power profiles. Using common ESD and power rail design methodology, the interface IP enables seamless pad ring integration and significantly reduce reliability risks. ARM also offers industry leading highly integrated, full speed DDR PHY solutions with at speed BIST and DFI support for flexible memory controller integration along with Specialty I/O such as LVDS physical interface.