Achronix announces PCI-SIG compliance for hardened PCI Express on Speedster22i FPGAs

SANTA CLARA, USA: Achronix Semiconductor Corp. announced that its 22nm Speedster22i devices have achieved PCI-SIG compliance with the PCI Express (PCIe) 3.0 Specification for x8 lanes.

The Speedster22i devices successfully passed the PCI-SIG Compliance and Interoperability Tests at the PCI-SIG workshop and are now included in the PCI-SIG integrators list. Based on Intel's 22nm Tri-gate technology, Speedster22i devices are the only FPGAs shipping today that contain a wide range of embedded hard IP - including PCI Express Gen3 with integrated DMA Engine, DDR3, 100G Ethernet and Interlaken.

Hardening key interface IP in the Speedster22i devices frees up a substantial portion of the programmable logic fabric, increasing the effective capacity of the FPGA and reducing the overall power consumption. Additionally the embedded hard IP in Speedster22i HD FPGAs eliminates the cost of purchasing, integrating, closing timing and testing the functions that are required when soft IP is used.

The PCI Express logic cores used in Speedster22i devices support Gen 1, 2 and 3 in x1, x4 and x8 configurations and are supplied by Northwest Logic. Speedster22i HD devices are the only FPGAs with an integrated DMA engine hardened as part of the PCI Express core. This provides additional cost, performance and power advantages vs. a soft implementation.

"We embedded the Northwest Logic PCI Express IP because it is an industry-leading, silicon-proven solution," said Steve Mensor, VP of Marketing at Achronix. "Our customers require fully proven functional solutions and that's what we are delivering with the embedded IP in our 22nm Speedster22i devices."

"Our PCI Express IP has been successfully deployed in hundreds of applications in both hard and soft implementations," said Brian Daellenbach, president, Northwest Logic. "We are excited to see our IP play a role in the Speedster22i success story."