MOUNTAIN VIEW, USA: Synopsys Inc. unveiled improvements to its HSPICE core engine technology that boost performance for complex analog and mixed-signal designs. In addition, new multi-threading capabilities in the March 2008 release of the HSPICE simulator speed up circuit simulation by taking advantage of new multi-core computer architectures.

As a result, circuit designers can now run HSPICE post-layout simulations up to three times faster on single-core processors and up to six times faster on four-core processors.

The newest version of the HSPICE simulator delivers improvements in the symbolic DC operating point convergence algorithm, transient time-step control, netlist parsing and model performance. These enhancements accelerate overall simulation throughput on single-core computers.

Previously, HSPICE multi-threading capabilities allowed circuit designers to quickly simulate large pre-layout designs. With the March 2008 release, Synopsys has extended HSPICE multi-threading capabilities to enable simulation of large post-layout designs containing in excess of a million resistive and capacitive parasitic effects.

As a result of these enhanced multi-threading simulation capabilities, fully extracted post-layout designs can now be simulated in just hours instead of days.