Dubai an emerging silicon frontier

Dubai an emerging silicon frontier

The government of Dubai has set up the Dubai Silicon Oasis Authority (DSOA) as the engine for propelling Dubai into the knowledge economy

Pradeep Chakraborty

Friday, May 23, 2008

Technology hub
The DSO is fast becoming a hub for technology R&D activities in the region, and is also the home of regional HQ of major electronics companies. It currently has 119 tenants, as of early May 2008.

The entire ecosystem is being built within the DSOA. It is an emerging residential area, and will also be home to RIT Dubai, BITS Pilani Dubai, and GEMS Smart School. Add to this theme parks, golf clubs, seven-star hotels, etc. It is more of a fully 'integrated city" purpose built by the government of Dubai, where its residents can work, live, learn and play.

Some tenants at DSOA, Dubai

Silicon and other activities
A variety of activities are promoted at the DSOA. In the microelectronics domain, there are activities related to IC design, EDA tools, semiconductor manufacturing, semiconductor assembly & test, as well as photovoltaics (PV).

Other general activities, not covering the semiconductors, include IT and IT security, telecom equipment, electronic and computer hardware, software development and solutions, nanotechnology, consultancy and business development, logistics, as well as talent development and recruitment.

The DSOA also houses the German Business Park and the Rochester Institute of Technology (RIT), Dubai. It has also made alliances with Synopsys, the EDA powerhouse, the American University of Sharjah, UAE University, University of Sharjah, BITS Pilani Dubai and Khalifa University.

The key business benefits of aligning with the DSO include access to a regional pool of talent, zero tax policy, competitive operating costs, and access to a regional market of 2 billion people. It also offers diverse support for creating R&D centers of Excellence.

Dubai Circuit Design
The Dubai Circuit Design (DCD) is one of the tenants within the DSOA with a vision to be the regional leading force for chip design innovation. DCD aims to provide customers with predictable chip design services and create a collaborative environment for its skilled engineers, which fosters creativity and innovation, while empowering them with the DSOA's state-of-the-art computing infrastructure.

The DCD incidentally has an alliance with Synopsys. It allows the DCD to have easy access to cutting-edge EDA tools, IP, wide range of resources, as well as Design Sphere Access (state-of-the-art data center).

The 10-member chip design team at the DCD comprises various nationalities -– India, Morocco, Tunisia, Egypt -- has Burj Al Arab, Dubai

already taped out one 65nm design. The team itself comes from leading semiconductor companies, such as Intel, Texas Instruments, Qualcomm, Wipro and ST Microelectronics, with an average experience of eight to 10 years.

The design team is experienced in areas such as front-end design, back-end physical design, design flow methodology, design for testability (DFT), etc.

The DCD offers a variety of IC design services (RTL to GDSII), supporting all technology nodes -- 65nm and below. It also has strong expertise in designing complex, multi-million gate, low power and performance-critical designs. DCD can also undertake foundry interface on behalf of the customers.

It also offers consultancy -- on-site or from the design center. This includes areas such as complete DFT solution, physical design, timing/power signoff, physical verification, reliability verification and extraction, full-chip feasibility analysis and area reduction, IP integration, full-chip feasibility analysis and area reduction, etc.

The DCD design team has done an SMC (scalable metrics chip) implementation. This was done using TSMC's 65nm low power (LP) technology. The encryption/decryption engine has ~ 8 million gates with 70 memory macros.

Other details of the project include dual core voltage (1.2v/0.96v) and IOs at 3.3v, wire bond design with 172 pads, 3.5x3.5 mm2 die size, 333Mhz/100Mhz design speed, as well as DFT (scan, ATPG, memory BIST, JTAG test interface).

©CIOL Bureau

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