BANGALORE, INDIA: Some time in December 2008,
Cadence Design Systems launched the
Cadence Encounter Digital Implementation System, a configurable digital implementation platform delivering incredible scalability with complete support for parallel processing across the design flow.
In an interaction with Rahul Deokar, Product Marketing Director, Cadence, we attempt to find out more about Encounter and whether it takes on Synopsys' Galaxy Custom Designer. Excerpts:
CIOL: What exactly can the Encounter Digital Implementation System do? And, why now? Will this take on Synopsys?
Rahul Deokar: The new "Encounter Digital Implementation System" is a next generation high-performance, high-capacity RTL-GDSII design closure solution with the industry's first End-to-End Parallel Processing flow that enables all steps of the design flow to be multi-CPU enabled: from floorplanning, placement, routing, extraction to timing and signal integrity signoff.
At its core is a new memory management architecture and end to end multi-CPU backplane that provides scalability with increased performance and capacity to reduce design time and time-to-market.
Yes, it surpasses the other solutions available in the marketplace based on the following capabilities and features:
* Ultra-scalable RTL-to-GDSII system with superior design closure and signoff analysis for low-power, mixed-signal, advanced node designs.
* End-to-end multi-core infrastructure and advanced memory architecture for unparalleled scalability of capacity, design turnaround time, and throughput.
* Robust design exploration and automated floorplan synthesis and ranking solution.
* Embedded signoff-qualified variation analysis and optimization across design flow.
* Integrated diagnostic tools for rapid global timing, clock and power analysis/debug.
Here's a list of benefits that it provides designers:
* Significantly reduces design time, schedule and development risk
* Increased productivity through automation; superior quality of results
* Configurable and extensible platform that ensures maximum utilization and ROI; upgrades proven design flow and amplifies existing expertise.
* Interoperability across package, logic, custom IC design, and manufacturability
CIOL: According to Cadence, it provides complete support for parallel processing across the design flow. Does this mean that designers can fully harness the power of multicore computing?
RD: Yes, the End-to-End Parallel Processing Flow is supported across the entire design flow and consequently, designers can fully harness the power of multicore computing. Today's designers commonly have Dual CPU or even Quad CPU machines on their desktop. The Encounter Digital Implementation System allows designers to leverage their multi-CPU hardware and gain significant TAT improvements on the design cycle time and overall development schedule.
The new Encounter end-to-end Multi-CPU backplane delivers Ultra-Scale Performance gains up to 16X in key areas like routing and timing closure. All steps of the design flow are multi-CPU enabled: from floorplanning, placement, routing, extraction to timing and signal integrity signoff. For instance, on a production design, when the Encounter Digital Implementation System is run on four CPUs, you can get a 3.2X performance boost across the entire, end-to-end design flow.
CIOL: Designers are said to be reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices. By what factors, and against which other tool(s) has this been rated?
RD: Cadence's Encounter Digital Implementation System has been developed working in close collaboration with over 15 customer partners who have extensively used, validated and now, deployed it. Customers are already seeing overall design cycles significantly shorted by 25-30 percent, which translates to multiple weeks or even months. These significant improvements are against competitive tool flows in their current methodology.
CIOL: What exactly is meant by "Encounter offering new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow"?
RD: Large scale design complexities (Increased functionality, Predictability, Productivity) pose one of the biggest challenges. Designs are getting huge at 100M + gates, 100+ Macros in the design, putting significant requirements on design tools, particularly, floorplanning of these macros and the whole design becomes a huge challenge.
The new Silicon Virtual Prototyping capabilities of Automated Floorplan Synthesis and Die Size Exploration help out exactly on that front. These can quickly provide floorplanning for that large 100M + gates, 100+ Macro design. And not just one floorplan, but designers can provide multiple criteria (say along the lines of timing or power or area or congestion) and you will get multiple floorplans with their rankings; and all this in a matter of minutes.
Essentially, you could finish your breakfast or lunch (depending upon how fast you eat!) and be back to have multiple floorplans that you can then pick and choose from...and then proceed to implementation.
