Cadence on Galaxy vs. Virtuoso and EDA trends

EDA Tools

Cadence on Galaxy vs. Virtuoso and EDA trends

According to Cadence, it defined a unified solution long ago, and its leadership in this area is testament of the company's vision

Pradeep Chakraborty

Monday, October 13, 2008

BANGALORE, INDIA: Cadence Design Systems has been the established leader in custom IC design space for 19 years. It has been constantly improving and upgrading technology to ensure that the EDA leader is providing the best software available for designing today's complex custom chips.

A couple of years ago, Cadence introduced the next-generation Virtuoso custom design IC 6.1 platform, which had a major upgrade recently with the IC 6.1.3 release. This release has been production-proven with tapeouts from many customers. However, it is Synopsys' Galaxy Custom Designer doing the rounds in the EDA circles as of now.

According to Sandeep Mehndiratta, Product Marketing Group Director, Cadence Design Systems: "From what we've read and heard from some of our mutual customers, the competitive introduction may be attempting to replicate older custom IC technology. While the jury will probably be out for some time on this unproven tool, Cadence continues to provide a complete solution for design, verification and implementation of complex analog and mixed-signal designs, differentiated by the tight integration between the underlying technologies."

This solution is built upon Cadence's decades of experience in this area and a strong eco-system made up of partners, third-party providers and foundries.

I engaged Mehndiratta on a range of issues, such as how the Synopsys' Galaxy Custom Designer matches up with the Virtuoso, and whether designers can now design what they wish, including concepts and flows, as well as the relevance of open architectures. Excerpts from an interview:

CIOL: How does the Galaxy Designer match up to the Cadence Virtuoso and vice versa?

Sandeep Mehndiratta: Cadence has been the established leader in custom IC design space for decades and we are constantly improving and upgrading our technology to ensure we are providing best-in-class platform for designing today’s complex custom chips.

A couple of years ago we introduced the next-generation Virtuoso custom design IC 6.1 platform. This release has been production-proven with tapeouts from many customers. Some of the leading customers that have adopted the Virtuoso platform include Ricoh, National Semiconductor, Cambridge Analog Technologies Inc., Matsushita, etc.

Synopsys has recently launched Galaxy Designer and it is unproven as yet. From what we've read and heard from some of our mutual customers, the competitive introduction may be attempting to replicate older custom IC technology. While the jury will probably be out for some time on this unproven tool, Cadence continues to provide a complete solution for design, verification and implementation of complex analog and mixed-signal designs, differentiated by the tight integration between the underlying technologies.

CIOL: With this development, is it safe to say that designers can now design what they wish, including concepts and flows?

SM: Cadence's solution is built upon our decades of experience in this area and a strong eco-system made up of partners, third-party providers and foundries.

Cadence introduced the next-generation Virtuoso custom design IC 6.1 platform a couple of years back. Virtuoso is the most complete eco-system for designing ICs; not only with its inherent flow, but also because of its linkages to multiple tools inside and outside of Cadence.

For many years, we have provided a consistent front-to-back flow, and over that time we have learned much about what customers need to do their designs efficiently. It is that knowledge base that we leveraged to accelerate productivity with 6.1 release couple of years back.

CIOL: Why has it taken so long for a first modern-era mixed-signal implementation solution to be in place?

SM: Cadence introduced next generation Virtuoso 6.1 in November 2006, which was the first modern, and most complete custom design solution released natively on the OA database, which was created and donated by Cadence. The productivity benefits are significant. RFIC Solutions Inc., a third-party intellectual property and design service provider, has increased productivity two-fold by adopting the Cadence Virtuoso custom design platform.

INSIDE Contactless, a fabless company and leader in contactless technology providing high-performance chipsets for secure, fast and reliable transactions with electronic identification, has saved 20 percent in development time by adopting Cadence Virtuoso UltraSim Full-Chip Simulator, a component of Virtuoso Multi-Mode Simulation with a high-performance digital-solver technology, for the verification of its current and next-generation contactless and Near Field Communication (NFC) system-on-chip (SoC) designs.

Specifically, mixed-signal design is evolutionary, not revolutionary. The concept of mixed-signal design isn't new. People have been designing in this manner for 15+ years. What is new is the more holistic approach being taken by designers developing mixed-signal circuits. The once clear lines between analog and digital design are blurring, and now the idea of "mixed-signal" is being architected in right from the beginning.

That is why Cadence's AMS Designer covers transistor to system level design with a single simulation solution for complete verification. It is why Cadence has combined the power of its leading implementation platforms (Virtuoso and Encounter) to handle the implementation of mixed-signal designs.

CIOL: Galaxy Custom Designer can provide a unified solution for custom and digital designs, thereby enhancing designer efficiency. How will this change/affect a) designing, and b) EDA landscape?

SM: Cadence defined a unified solution long ago. Our industry leadership in this area, and Synopsys mimicking of that solution are testaments of Cadence’s vision.

Competition is good for all industries, the end-customer usually benefits. You can count on Cadence to not only remain competitive, but also retain our industry leadership in custom/mixed-signal design.

CIOL: How important is open architecture that natively supports interoperable PDKs?

SM: Cadence believes in open architectures. Design Framework II was built as an open architecture, which is why there are many companies that have connected (30+) to form a larger ecosystem. Whereas, the Industry Standard Framework has been tried and failed.

The reason it was a failure is the same as interoperable PDKs. Building frameworks and PDKs that are based on a "lowest common denominator" principle do not provide the most optimized design flow. Instead, you are left with systems that try to please everyone and in the end are rejected as bloated beasts retarding the progress of design.

CIOL: While on open architecture and interoperable PDKs, so why has it taken so long for the EDA industry to reach this stage?

SM: The concept has been tried before and rejected for the reasons discussed earlier.

CIOL: How does Cadence propose to address this challenge?

SM: By continuing to provide our customers and partners with a framework in which they can build their tools into the Virtuoso design flow in the most optimized way possible.

Also, by providing our proven and industry standard Pcell technology that takes advantage of the key features in our design flow, allowing for fast and productive design today and in the future.

©CIOL Bureau

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NYC said on 10/15/2008 5:01:02 AM:
Each of the customers mentioned in the article do have press releases with Cadence talking about the productivity they have achieved using the latest Cadence software. If you are interested in facts rather than innuendo and speculation, I invite you to the Cadence.com website to read more about it.

to NYC

Ed said on 10/13/2008 5:30:33 PM:
The link which says National Semiconductor has Synopsys as its EDA partner is within this story.

to Ed

PC said on 10/13/2008 5:29:04 PM:
Thats correct! Nat Semi has indeed selected Synopsys as its key EDA partner

to PC

David Muncier said on 10/13/2008 5:22:21 AM:
Cadence is in deep trouble if they really believe this mantra - open inter-operable PDKs will sink their quasi-monopoly based on proprietary PDKs. In current financial environment, customers will leave Virtuoso in a pico-second if they can get similar or better functionality in an open solution. I think National Semiconductor has already gone over to Synopsys in July.

to David Muncier

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