RD: The main customers include semiconductor companies working on leading-edge 45- and 32-nanometer designs, with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content. 

The challenges facing these designs comprise of an increasing demand for design tool performance/capacity and design features for challenging ultra-large scale designs in the areas of low power, mixed signal, advanced node and signoff analysis. In addition, small market windows and product life-cycles and the cost pressures further exacerbate the situation.

The Encounter Digital Implementation System’s core design closure capabilities plus the new advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization provide comprehensive manufacturing-aware and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure even on the most challenging designs.

CIOL: What kind of work has gone into reducing the memory footprint of the most memory-retentive applications?

RD: At the core of the new Encounter System is an innovative memory architecture that enables capacity and performance Gains of 30-40 percent for full flat and hierarchical designs, even if you are running on a single-CPU machine. The R&D team has developed an advanced memory defragmentation algorithm that allows the applications to be extremely memory-frugal …and that memory-efficiency enables designers to handle their biggest 100M+ instance designs.

CIOL: There are parallels with Synopsys' Custom Designer for AMS. How true? Also, there seem (there will) to be every chance of Virtuoso and Encounter coming together. Pl. comment.

RD: Synopsys’ Custom Designer for AMS is their entry into the full-custom/analog design marketplace, where the Cadence Virtuoso platform is a strong incumbent.

The biggest challenge for mixed signal designers today is the efforts/resources involved in taking design data from the full-custom/analog tools to the Digital Implementation tools...and back and forth…in never-ending iterations.
 
Now, with the new Encounter Digital Implementation System, designers get the seamless full-custom/analog and digital design implementation interoperability…with unified constraints handling, mixed-signal floorplanning and ECO. It executes off a common design database (OpenAccess), enabling edits made in one design environment (e.g. Virtuoso) to be easily seen in the other design environment (e.g. Encounter).

It also enables the design team to easily transfer the design data, to determine the optimal floorplan based on analog and digital constraints. For example, the analog design team moves pins on the analog block, when the design is opened in Encounter, the modified pin locations are easily seen and the digital design team can execute a pin optimization to re-align the pins at the top-level.

In addition, the user can enter routing constraints in either Encounter or Virtuoso, and implement mixed signal routing in either environment. Top-level routing constraints could be defined within Virtuoso, then the top-level routing completed using the mixed signal routing functionality within Encounter.

And customers are already seeing their overall design schedules significantly reduced.

CIOL: Elaborate on the DFM practices embedded throughout the end-to-end parallel processing flow.

RD: At 45nm, random and systematic process variability is a significant cause of yield loss, lower performance and higher power consumption. Manufacturing effects (Lithography, CMP, etch, and statistical process variations) need to accounted for. These impact not only the printability and design rules but also induce electrical variability. You could have 20-30 percent difference in timing in your design or 300 percent variation in leakage power in your design.

The new Encounter Digital Implementation drives design yield and performance higher with a comprehensive manufacturability-aware solution that encompasses systematic (lithography, CMP, thermal) and statistical timing and leakage power analysis as well as optimization…leveraging the end-to-end parallel processing flow.

The new Encounter system handles all the regular requirements like 32nm design rule support, via reduction and via-doubling, and the physical impact of manufacturing. The key difference is that the manufacturing effects are not an after-thought but Encounter takes a prevention, analysis and repair approach within digital Implementation.

For instance, the embedded Litho-hotspot prevention capability can address majority of the potential Litho violations very early in the design flow. Also, Encounter uniquely accounts and optimizes for the manufacturing impact on timing, SI and power.