SAN FRANCISCO, USA: Tier Logic Incorporated has given out the first details about its technology, which employs a new processing change to build FPGA and ASIC products on a single die.

In a statement, Tier Logic said its technology depends on a 3-dimensional structure. The company has explained that its approach separates user circuits and configuration circuits into 3-D stacked layers – thus creating what it claims to be the world’s first monolithic 3-D FPGA.

The 3-D TierFPGA of Tier Logic has one level (or, tier) of thin-film transistor (TFT)-based SRAM, which creates a more efficient device than a traditional 2-D FPGA, a majority of which is configuration SRAM.

Paul Hollingworth, vice-president (sales and marketing) of Tier Logic, said in the statement that the company’s FPGAs are converted to ASICs by replacing the TFT SRAM top layer containing the programmable configuration circuitry with a simple metal layer by retaining the identical timing. 

The greatest advantage of the device’s structure, according to Paul Hollingworth, is that it enables TierFPGAs to be converted to ASICs rather quickly and painlessly by just replacing the TFT SRAM with metal.

He added that, unlike any other type of ASIC conversion, the Tier Logic timing remains identical between the FPGA and ASIC – thus allowing zero-risk and zero-effort conversions.