Synopsys intros DDR3/DDR2 IP solns for SoCs

Synopsys intros DDR3/DDR2 IP solns for SoCs

High-performance DesignWare IP supports speeds up to 1600Mbps

Thursday, August 14, 2008

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of a full range of silicon-proven DesignWare DDR IP solutions for systems-on-chips (SoCs) that require an interface to high-performance DDR3, DDR2 and DDR memory subsystems.

The DesignWare DDR IP solutions deliver memory system performance of up to 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification. The solutions include configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os and verification IP. The DesignWare DDR IP portfolio provides designers with scalable solutions that help reduce risk and speed time-to-market for applications such as digital home, digital office, data center and storage.

The comprehensive DesignWare DDR IP portfolio consists of three product lines including DDR3/2, DDR2/3-Lite and DDR2/DDR, all of which have been validated and fully characterized in Synopsys' silicon test chips and support two generations of DDR SDRAM:

* The DDR3/2 IP helps satisfy the needs of the highest performance interfaces with operation at up to 1600 Mbps and offers a wealth of in-system calibration capabilities to ease implementation of the interface at higher data rates.

* The DDR2/3-Lite IP is an area- and feature-optimized IP solution operating at up to 1066 Mbps using DDR2 or DDR3 SDRAMs. The DDR2/3-Lite IP is ideal for SoCs that initially target DDR2 SDRAMs, and has the option of migrating to DDR3 when it becomes more cost effective without the need to modify the current SoC design.

* The DDR2/DDR IP operates at speeds up to 1066 Mbps and is available in leading 130nm, 90nm and 65nm process technologies.

The DesignWare DDR IP provides designers with the flexibility to interface to DRAM components or dual in-line memory modules (DIMMs) including support for write/read leveling as required with DDR3 DIMMs. To further configure a memory interface that is unique to each SoC, the DesignWare DDR IP permits customization of DRAM interface width, number of DRAM ranks, power I/O to signal I/O ratios, and flexible I/O placement as required by the SoC package.

Each of the three DesignWare DDR IP product lines consists of a complete solution including configurable memory and protocol controllers, integrated PHY and verification IP. Unlike other DDR controller solutions, Synopsys offers designers a choice of two digital controllers. The DesignWare DDR Memory Controllers support up to 32 on-chip application buses, quality of service (QoS)-based arbitration and optimized memory transaction scheduling.

The DesignWare DDR Protocol Controllers, a unique offering, provide efficient DDR control and protocol translation allowing customers to implement their own optimized custom memory scheduler. Complementing the digital controllers are the integrated, hardened PHYs, which include the application specific I/Os, DLLs, PLLs and other PHY logic, significantly easing timing closure in the SoC design flow and within the timing budget for the overall DRAM interface.

The DesignWare DDR3/2, DDR2/3-Lite and DDR2/DDR IP solutions are available now. The DDR PHY IP is available in leading 130nm, 90nm, and 65nm process technologies.

©CIOL Bureau