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Using this engine, engineers can evaluate the chip and make early-stage modifications to provide a better starting point for physical implementation, reduce or even eliminate iterations between synthesis and physical implementation, and accelerate the design cycle.
"Our goal is to help customers increase their ability to achieve first-pass silicon success," said Stephen Fu, deputy director of the IP and Design Support Division at UMC. "Our ongoing collaboration with Synopsys has helped us develop this validated 65-nm reference flow and we expect this will help reduce design risk, lower power consumption, and reduce turnaround time for our customers."
The reference flow also includes automatic level shifter insertion, placement, optimization and verification. Voltage area (VA) creation, power-switch cell insertion, VA-aware physical optimization, clock-tree synthesis and routing are utilized to reduce dynamic power consumption.
The multi-voltage timing flow closure includes signal integrity (SI) prevention,repair and signoff, and multi-voltage analysis. Additional DFM features include redundant via insertion, via-farm/via-array rules, and timing-driven metal fill.
Synopsys Professional Services and UMC engineers validated the reference flow using the test chip tape-out for "Leon," an open-source 32-bit RISC microprocessor core. The test chip was partitioned into multiple voltage regions using the advanced, low-power reference flow. UMC also utilized its own internally developed library for its 65-nm design process.
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