Rambus demos XDR memory system

Rambus demos XDR memory system

The company has said in a communication that the silicon demonstration comprised Elpida's recently-announced 1Gb XDR DRAM device and an XIO memory controller transmitting realistic data patterns

Monday, June 29, 2009

BANGALORE, INDIA: Rambus Inc, the technology licensing company which is into high-speed memory architecture, has said it has showcased a silicon demonstration of a complete XDR memory system running at data rates up to 7.2Gbps with superior power efficiency.

The company has said in a communication that the silicon demonstration comprised Elpida's recently-announced 1Gb XDR DRAM device and an XIO memory controller transmitting realistic data patterns.

The XIO memory controller is up to 3.5 times more power efficient than a GDDR5 controller, and the total memory system can provide up to two times more bandwidth than GDDR5 at equivalent power. In addition, the XIO memory controller demonstrated bi-modal operation with support for both XDR DRAM as well as next-generation XDR2 DRAM.

The demo at Denali MemCon 2009 in San Jose, marked the first implementation supporting the XDR memory architecture roadmap incorporating innovations developed as part of Rambus' Terabyte Bandwidth Initiative. The innovations, which have been implemented in the bi-modal XIO memory controller for XDR2 operation, include Fully Differential Memory Architecture (FDMA) that enhances signal integrity and increases performance through point-to-point differential signaling of clock, data, and command/address; FlexLink that reduces pin count and increases scalability; and Enhanced FlexPhase that enables the world's highest memory signaling rates while simplifying routing and board design.

The company said that built on these innovations, an XDR2 memory system can provide memory bandwidths of over 500GB/s to a SoC. A single 4Byte-wide, 9.6Gbps XDR2 DRAM device can deliver up to 38.4GB/s of peak bandwidth, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s.

The XDR and XDR2 memory architectures would be scalable across a broad range of performance appropriate for multi-core computing, graphics, gaming, and consumer electronics, it added.

©CIOL Bureau