FPGA design verification easier more economic

FPGA Verification

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FPGA design verification easier, more economic

Real Intent introduces Meridian FPGA; popular clock domain crossing verification software for Altera customers

Sunday, November 09, 2008

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SAN JOSE, USA: Real Intent Inc., a leading supplier of verification software for electronic design, announced its first release of Meridian FPGA verification software.

Meridian FPGA is specifically designed to work with Altera Corp.'s latest release of its Quartus II software, version 8.1, to verify Clock Domain Crossings (CDC). It offers a cost-effective alternative when compared to the cost of equivalent ASIC design software.

Meridian FPGA enables 4X faster CDC closure through automatic, template-free and powerful clock intent verification. It verifies FIFO and Protocol-driven CDC interfaces for maximal confidence. Effects specific to FPGA platforms are automatically integrated in the verification process. Meridian FPGA is tightly integrated with Quartus II software to deliver verification confidence in a seamless flow.

"Reliable CDC verification is a growing problem for FPGA designers," said Prakash Narain, CEO of Real Intent. "We have always supported both ASIC and FPGA designs. By integrating Altera's Quartus II software with Meridian FPGA, we are giving our mutual customers access to powerful CDC verification technology, making it easier and economic to produce reliable FPGA designs."

"As the functionality of FPGAs increases, a greater level of importance is placed on verification tools that quickly demonstrate the accuracy of the user's design," said Jim Smith, director of EDA vendor relations at Altera. "Real Intent's Meridian FPGA verification software complements the productivity benefits of our Quartus II software by helping speed the verification process and minimize overall FPGA development time."

©CIOL Bureau

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