BANGALORE, INDIA: Reaffirming its leadership position in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs, Altera Corp. today unveiled Quartus II software version 8.1.

This latest release of Quartus II software continues the company’s history of delivering high-density FPGA compile times three times faster than other FPGA-vendor supplied development software, based on internal benchmarks. The enhanced productivity features within Quartus II software enable design teams to close timing and power faster, lower R&D costs and shorten time to market.

“Managing design time and engineering resources is an increasing concern for companies using the latest deep-submicron FPGA technologies in their next-generation systems,” said Bryan Lewis, chief analyst with market research firm Gartner. “The shrinking process geometries of FPGAs, combined with their increased functionality, necessitate the need for sophisticated tools that allow design teams to maximize their productivity and meet critical time-to-market goals.”

“Customers using our high-speed data acquisition boards rely on Acquisition Logic to quickly deliver solutions that process data in real time, which is why we leverage Altera’s FPGA technology,” said Michael Wyrick, vice president of engineering, Acquisition Logic.

“While our FPGA-based systems demand higher performance and lower power, our market windows remain just as stringent. Quartus II software provides us with the best environment to get our FPGA designs completed efficiently. Using Altera’s design software, we are able to close timing quicker, meet our power budgets and fully maximize the performance benefits of our Altera device, all without increasing our FPGA development time.”

Faster design development
While next-generation FPGAs deliver a greater level of functionality, design teams continue to be constrained by limited development times. Quartus II software version 8.1 helps speed development times by automating traditionally time-consuming features. The design partition planner, introduced in the previous version of Quartus II software, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation.

Quartus II software now also eliminates the need to modify gated clocks manually by automatically converting gated clocks to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.

Expanded device support
Altera cemented its leadership position in the high-performance, high-density FPGA market with the launch of its 40-nm Stratix IV FPGAs in May 2008. To date, nearly 600 customers are part of Altera’s Stratix IV early adopter program, and many have started designing Stratix IV FPGAs into applications across all of Altera’s market segments using Quartus II software.

Version 8.1 provides an even greater level of support to these customers by adding Stratix IV pin-outs and support for a new Stratix IV FPGA speed grade offered in a low-cost package. The software provides added transceiver timing-model support, as well as support for 8.5-Gbps transceivers, 1.6-Gbps LVDS and 400-MHz DDR memory. For designers targeting a HardCopy ASIC implementation, Quartus II software provides initial support for HardCopy IV ASICs.

“Altera continues to set the pace for enabling designer productivity,” said Chris Balough, senior marketing director for software, embedded and DSP at Altera. “This latest version of Quartus II software continues our tradition of delivering productivity leadership while maintaining our 3X compile-time advantage for high-density FPGAs.”

New features
SignalTap II Embedded Logic Analyzer: Finer data-sampling control speeds debugging and improves on-chip memory efficiency.
Enhanced SOPC Builder Tool
* New HDL templates enhance the speed and ease for which SOPC Builder can be used for intellectual property (IP) reuse.
* A new Avalon memory-mapped half-rate bridge is available for low-latency access for DDR SDRAMs.
New operating system support: Red Hat Enterprise Linux 5 and CentOS 4/5 (32 bit/64 bit) are now included.
Enhanced third-party simulation interface: The interface supports automatic compilation of library files for faster simulation setup.
New Pin-Out Advisor: The advisor guides pin-out creation and interface with third-party board tools.
Real Intent Verification Support: Real Intent’s Meridian FPGA Clock Domain Crossing (CDC) software offers easy-to-use automatic clock intent verification to catch design errors and create confidence in reliable CDC operations.
New and enhanced IP cores and megafunctions: Digital signal processing (DSP), memory and protocols accelerate development.
Physical synthesis engine enhancements: Improve performance of timing-critical blocks in 20 percent less time on average than the previous version for faster timing closure.
Synopsys Design Constraints (SDC): SDC templates guide and accelerate timing constraint creation.
 
Pricing and availability
Both the subscription edition and the free web edition of Quartus II software version 8.1 now are available for download. The Subscription Edition is also available in DVD format by request. Altera’s software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment.

Subscribers receive Quartus II software, the ModelSim-Altera edition, and a full license to the IP Base Suite, which includes 11 of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera’s eStore or from authorized distributors.