SANTA CLARA, USA: Sequence Design has introduced the PowerArtist, offering the industry's fastest automated RTL power reduction - 10-50 percent or more depending on the design - in just minutes on a million-plus gate block. Unlike approaches limited by design size, PowerArtist has run on a 15M gate design in four hours within a 12GB footprint. PowerArtist will begin shipping Q2, 2008.

Built upon the foundation of proven Sequence RTL DFP (Design For Power) accurate power analysis technology, PowerArtist focuses on trimming power in three key areas: clock, memory, and datapath at RTL where designers have maximum opportunities for power reduction. The power savings are over and above those achieved during synthesis.

Next-generation engines examine the RTL code, prioritize power reductions, and either maximize power savings automatically or guide the user through manual edits within a powerful graphical environment, Sequence's new PowerCanvas GUI. The RTL changes preserve the original RTL formatting by only making precise, surgical changes to the code.

"In an already power-optimized processor design, PowerArtist helped us identify 20 percent additional clock power reduction opportunities," said Jon Gibbons, Ubicom Vice President of VLSI Engineering. "By finding ways to reduce power in clock, memory, and datapath, and then highlighting the precise RTL code we needed to change, PowerArtist can provide us with a huge productivity gain."

PowerArtist integrates with all standard design flows, including synthesis and formal verification. It allows users to automate proprietary power reductions using the Si2 OpenAccess database with its open API.

"Great artists require two things to create their masterpiece: inspiration and superior equipment. With PowerArtist, designers will now have an RTL power-reduction tool worthy of their skills," said Sequence president and CEO, Vic Kulkarni.

PowerArtist is built upon Sequence's industry-leading power-analysis technologies, and significantly increases productivity by offering the flexibility to either pinpoint and manually edit RTL, or reduce power automatically with multiple techniques.

Clock power reduction
As much as 60 percent of SoC power consumption can be the clock power. PowerArtist employs multiple techniques to automatically reduce clock power and generates constraints to drive synthesis for power-smart and additional clock gating. Unlike synthesis, PowerArtist can quickly analyze the registers lacking enables for which it either finds or creates enable signals. It also analyzes signal activity over time to determine the power-efficiency of enables and identify the registers for synthesis to clock gate. PowerArtist automatically considers power in clock trees at the RTL to determine the effectiveness of RTL changes.

Memory power reduction
Memory power can account for half of an SoC's power consumption. PowerArtist is the only solution for reducing memory power at RTL by gating memory clocks, memory splitting and uncovering extraneous memory activity. During early customer testing, PowerArtist realized 60 percent total power savings based on memory techniques alone for a networking design application.

Datapath power reduction
Datapath is a significant component of an SoC's power consumption. PowerArtist reduces power by identifying wasted datapath activity with a set of three techniques.

PowerCanvas advanced GUI
PowerCanvas provides a powerful interactive environment to graphically pinpoint and understand power reductions while managing RTL changes. Users can sort and filter results, cross-probe to schematic logic cones downstream and upstream, and accept or reject RTL changes.