Toshiba intros high-k/Ge gate stack tech

Toshiba intros high-k/Ge gate stack tech

The significance of the new innovation is that it can be put to use in the development of advanced metal-insulator-semiconductor field-effect transistors in future generations of LSIs

Tuesday, June 16, 2009

BANGALORE, INDIA: In what could be a forerunner in this field of technological advancement, Toshiba has developed a gate stack and interlayer with high carrier mobility.

The significance of the new innovation is that it can be put to use in the development of advanced metal-insulator-semiconductor field-effect transistors (MISFETs) in future generations of LSIs.

Elaborating on the new development, a source said Toshiba has come out with the new innovation in the form of an ultra-thin, equivalent oxide thickness (EOT)-scalable high-k/Ge gate stack with strontium germanide (SrGex) interlayer.

It boasts of high carrier mobility which, in fact, is a basic technology with potential for application in MISFETs at the 16nm node and beyond, the source added.

With the new development, the company has effectively rolled out a technology that overcomes the twin challenges of fabricating a thin gate stack while maintaining high hole mobility, by inserting SrGex, a compound of strontium (Sr) and germanium, as an interlayer between the high-k insulating layer and the germanium channel. Toshiba is expected to continue to develop the technology as an option toward implementation of Ge-MISFET to 16nm LSIs and beyond.

It may be seen that current MISFETs in the scene use silicon for the channel. However, hassles are such that limitations of silicon make it difficult to obtain sufficient drive current in future scaled down MISFETs. It is here that Germanium (Ge), long known as an alternative offering higher carrier mobility characteristics, comes into play.

It has, in the meantime, been found that significant technical challenges exist in implementing germanium in LSIs, which include development of gate stack structures for Ge-MISFETs. A report pointed out that Germanium is first subject to heat surface treatment in an ultra-high vacuum, and a layer of strontium of up to ten atoms is deposited on the surface of the germanium, followed by a lanthanum aluminate (LaAlO3) high-k film. The gate stack is then annealed in a nitrogen atmosphere. The SrGex layer is formed during these processes, between the high-k film and the germanium channel.

In effect, the Toshiba innovation brings in peak hole mobility of 481cm2/Volt second (Vsec), a record high value for high-k/Ge p-MISFETs. This, in fact, is more than thrice the value obtained without the SrGex interlayer, and over twice the universal mobility that can be realized with silicon.

©CIOL Bureau