MOUNTAIN VIEW, USA: Toshiba Corp. has signed a multi-year business agreement to establish Synopsys Inc. as its key EDA partner across the Toshiba semiconductor design flow.

As a result of the expanded relationship, Toshiba plans to expand use of Synopsys' verification and implementation design flow while partnering to reduce design cycle time.

"For longer than five years we have continued to build a successful relationship with Synopsys by collaborating across a broad set of next-generation EDA, commercial IP, and manufacturing technologies," said Tomotaka Saito, senior general manager of System LSI Division, Semiconductor Company, Toshiba Corp.

"The resulting products and design flow have enabled Toshiba to tape-out a number of chips across multiple technologies. Our existing Synopsys relationship helps solve current and future SoC design needs," he added.

The latest agreement between the two companies expands Toshiba's use of solutions across Synopsys' comprehensive portfolio. These products include Synopsys' Galaxy design platform featuring IC Compiler place-and-route technology, Design Compiler synthesis, DFT MAX test synthesis, TetraMAX automatic test pattern generation, PrimeTime timing analysis, Star-RCXT parasitic extraction, and IC Validator physical verification; Synopsys' Discovery verification platform featuring the VCS, HSPICE and CustomSim simulators for analog and digital verification; DesignWare Library; the Synplicity FPGA design solution; and the Eclypse Low Power Solution.