MOUNTAIN VIEW, USA: Synopsys Inc. announced that Renesas Technology Corp. has deployed Synopsys' PrimeTime advanced on-chip variation (OCV) capability to help accelerate timing closure for 65-nanometer (nm) and below system-on-chip (SoC) designs.

PrimeTime advanced OCV analysis is an efficient, easy-to-adopt solution that employs adaptive derating to accurately account for random and systematic process variations across an integrated circuit (IC). This evolutionary approach brings the margin reduction benefits of variation-aware modeling to a broader range of customers and process technologies by eliminating the need to change libraries or significantly modify design flows.

PrimeTime advanced OCV has been correlated to silicon at leading semiconductor companies including Renesas, qualified and recommended by the STARC Japanese semiconductor consortium, and is part of the stage-based on-chip variation solution in the TSMC Reference Flow 9.0.

Synopsys' PrimeTime advanced OCV technology provides more finely-tuned design margins in timing analysis by incorporating logic-depth information to determine path-specific and cell-specific margin values.

Using simple derate tables to complement the global derate methodology that has been used for many years to account for on-chip variation allows PrimeTime customers to take advantage of the more finely-tuned design margins with minimal changes to existing timing signoff scripts.

The PrimeTime advanced OCV capability is part of a comprehensive set of variation-aware design solutions offered by Synopsys that also includes the PrimeTime VX statistical static timing analysis (SSTA) tool. While mainstream designs can readily take advantage of the PrimeTime advanced OCV solution, the PrimeTime VX solution provides further benefits for high-performance designs targeting advanced process technology nodes.