AHMEDABAD, INDIA: Convergence of media and communication technologies is creating a new user experience. Digital video transmission has changed the way video had been delivered traditionally. High-quality video transmission is creating challenges to designers and this article tries to address how new generation chips address these challenges.

Background on multimedia and video compression
The tasks involved in any multimedia (audio-video) application can be thought of as:

1. Reception of multimedia data (through network, or  input video/audio ports)
2. Pre-processing of input data in case of analog audio-video inputs.
3. Extraction of elementary audio-video streams from different transport containers (RTP, MPEG-2TS, 3GP, QTFF etc) for decoder application.
4. Encoding/Decoding of video/audio streams (raw/compressed) with required audio-video encoder/decoder.
5. Post-processing of encoder/decoder output data.

Each task requires high CPU cycles and different instruction set architectures (ISA) in order to have real time encoding/decoding performance. For example, data path (instruction sets) required for extracting audio/video streams are very much different from that of signal processing operation (convolution/filtering operation). 

So, it is highly desired to have different sub system/core with different type of data path (instruction sets) optimized for specific jobs needed in multimedia application. New generation high performance media SoCs (System on Chip) incorporate such needs by having different sub systems for different tasks like RISC for OS/application control flow and DSP with hardware accelerator for encode/decode/signal processing operations.

These sub-systems are highly optimized in terms of data path for specific multimedia task (includes advantage of having ASIC for a particular task) which results in effective task level pipelining and increase in overall system performance.

Video encoding - challenges
Video encoding is one of the most challenging problems faced by current video chip designers due to very high computation complexity and data bandwidth requirements. This challenge gets compounded by a plethora of video standards and ever-increasing consumer demand for better quality through HD proliferation.

Due to complex compression standards like H.264/VC-1, it becomes difficult to achieve real time performance in the case of HD video (or higher resolution video) encode/decode using single DSP having general instruction sets. So some highly optimized h/w accelerators are also provided which offloads different modules of compression standards from DSP, like context adaptive bit stream code/decode, quantization, inverse-quantization, DCT, iDCT, motion compensation, motion estimation and inloop-filtering which require high CPU processing power. These h/w modules can run in parallel with DSP core so that it can be effectively pipelined with different jobs (like parsing, DCT, ME, MC etc.) which result in very high h/w module throughput.

Current scenario
Due to high processing power requirements, typically HD video encoding was performed using custom ASICs or FPGAs. Custom ASICs used to offer good processing capability at lower power. But, the volumes were not very high to bring down the price. Another challenge is support for only one standard. Typically, there are lot of ASICs for MPEG2 compression which had been quite popular for DVD players and movies.

With compression standards moving to H.264, MPEG4 or VC-1, the need for supporting multiple standards became more evident. This was accomplished using FPGAs or high speed or multi-core DSPs. FPGAs offer high performance, but come with a cost, design time and power consumption penalty. Multi-core and high speed DSPs also had the same problem of higher cost and power consumption.

New generation chips
Newer generation chips have to address three basic concerns of designers:

1. Should be programmable to support multiple compression standards
2. Lower cost and lower power consumption
3. Should have headroom for other DSP functions like Video Analytics apart from encoding

The new generation chips take advantage of both the DSP world and ASIC / FPGA world. They use hardware accelerators which perform parallel signal processing tasks compared to traditional sequential software processing in DSP. The chips contain three major blocks:

1. Hardware accelerators
2. Control processor
3. DSP Core

These chips address the concerns of designers and provide faster time to market at lower cost.

Typical example
The DaVinci-HD DM6467TM processor (from Texas Instruments) is a very high performance media SoC, which is highly customized for HD video application. The HD performance makes the SoC very suitable in equipments handling HD H.264/VC-1 video such as HD broadcast, HD video transcode, multi channel SD video encode and decode.

Chip features
* Single chip solution implementing multiple sub-systems tuned for real time, multi-format, HD video performance.
* Based on an ARM926EJ-S core, TMS320C64x+TM DSP core and HD video/imaging coprocessor.
* The HD-VICP is optimized for multi-format transcoding and provides 720p/1080i MPEG-2, H.264, VC-1, MPEG-4 encode/decode.

Performance
The DM6467TM SoC is designed to address the HD transcoding challenge for commercial and consumer markets. It supports multi format HD video (720p @ 60Hz, 1080i @ 60 Hz, 1080p @ 30 Hz) decode/encode, simultaneous multi channel, multi-format SD video decode and encode. For example, it can handle simultaneous 4-channel D1 resolution H.264 Main Profile @ 30 Hz video encode, 4xCIF H.264 Baseline Profile @ 30 Hz video encode and some video analytics application.

Cost, power consumption and performance advantages
The DM6467TM is available at 1/10 the cost of previous application system while addressing multiple formats HD video encode and decode. As the overall functionality is performed within single chip, overall power consumption comes down by a factor of four. Same form factor boards can accommodate more number of DSPs to support multi-channel video encode / decode and transcode applications.